Yifan Liu bae19f5f1f hv: riscv: Rework context save/restore assembly routine ...

Original interrupt context save/restore routine saves to/restore from
per-cpu stack. This commit modifies it to support saving to/restoring
from address pointed to by sscratch register.

When sscratch is 0, the assembly is functionally equivalent to the
old version (save to/restore from per-cpu stack)

When sscratch is not 0, the assembly saves to/restores from the place
that sscratch points to.

hstatus is also added to the trap frame as this affects the virtual
mode the trap returns to.

Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>

2025-11-14 10:44:41 +08:00

..

riscv

hv: riscv: Rework context save/restore assembly routine

2025-11-14 10:44:41 +08:00

x86

hv: multi-arch: include common IRQ header instead of arch-specific one

2025-11-05 15:14:41 +08:00