Haicheng Li bd0e83fa5f io: add risc-v mmio read and write APIs with memory order ...

Follow multi-arch, add risc-v MMIO APIs with memory order, without
PIO support.

Tracked-On: #8807
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Co-developed-by:  Fei Li <fei1.li@intel.com>
Signed-off-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>

2025-10-09 17:15:06 +08:00

..

asm

io: add risc-v mmio read and write APIs with memory order

2025-10-09 17:15:06 +08:00