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bdae8efb7f
There're some instructions which not support bit 0(w bit) flag but which memory opcode size is fixed and the memory opcode size is not equal to the register opcode size. In our code, there is movzx (which opcode is 0F B7) which memory opcode size is fixed to 16 bits. So add a flag VIE_OP_F_WORD_OP to indicate a instruction which memory opcode size is fixed to 16 bits. Tracked-On: #1337 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com> |
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| common | ||
| debug | ||
| dm | ||
| hw | ||
| include | ||
| lib | ||
| release | ||
| scenarios | ||
| scripts | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||
| README.rst | ||
ACRN Hypervisor ############### The open source `Project ACRN`_ defines a device hypervisor reference stack and an architecture for running multiple software subsystems, managed securely, on a consolidated system by means of a virtual machine manager. It also defines a reference framework implementation for virtual device emulation, called the "ACRN Device Model". The ACRN Hypervisor is a Type 1 reference hypervisor stack, running directly on the bare-metal hardware, and is suitable for a variety of IoT and embedded device solutions. The ACRN hypervisor addresses the gap that currently exists between datacenter hypervisors, and hard partitioning hypervisors. The ACRN hypervisor architecture partitions the system into different functional domains, with carefully selected guest OS sharing optimizations for IoT and embedded devices. You can find out more about Project ACRN on the `Project ACRN documentation`_ website. .. _`Project ACRN`: https://projectacrn.org .. _`ACRN Hypervisor`: https://github.com/projectacrn/acrn-hypervisor .. _`Project ACRN documentation`: https://projectacrn.github.io/