acrn-hypervisor/hypervisor/arch/x86/guest
Victor Sun 7647517a15 HV: trap and validate px request
Currently acrn partitions cpus between SOS and UOS, so the default
policy is to allow guest managing CPU px state. However we would
not blindly passthrough perf_ctrl MSR to guest. Instead guest access
is always trapped and validated by acrn hypervisor before forwarding
to pcpu. Doing so leaves room for future power budget control in
hypervisor, e.g. limiting turbo percentage that a cpu can enter.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
..
guest.c vm load: fix bug in loading kernel 2018-05-15 17:19:37 +08:00
instr_emul_wrapper.c initial import 2018-05-11 14:44:28 +08:00
instr_emul_wrapper.h hv: microcode: Enable microcode update from SOS. 2018-05-15 17:19:37 +08:00
instr_emul.c initial import 2018-05-11 14:44:28 +08:00
instr_emul.h initial import 2018-05-11 14:44:28 +08:00
time.h initial import 2018-05-11 14:44:28 +08:00
ucode.c cpuid restruct 2018-05-15 17:19:38 +08:00
vcpu.c initial import 2018-05-11 14:44:28 +08:00
vioapic.c initial import 2018-05-11 14:44:28 +08:00
vlapic_priv.h initial import 2018-05-11 14:44:28 +08:00
vlapic.c enable TSC-offset & add TSC MSR emulation 2018-05-15 17:25:23 +08:00
vm.c HV: setup px info when create vm 2018-05-15 17:25:25 +08:00
vmcall.c HV: add hypercall interface of get vcpu state data 2018-05-15 17:25:25 +08:00
vmsr.c HV: trap and validate px request 2018-05-15 17:25:25 +08:00
vpic.c vpic: use calloc to init vpic instead of malloc 2018-05-15 17:19:36 +08:00