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The VIRTIO_PCI_CAP_PCI_CFG capability creates an alternative access method to the common configuration, notification, ISR and device- specific configuration regions. To access a device region, the driver writes into the capability structure (ie. within the PCI configuration space) as follows: - The driver sets the BAR to access by writing to cap.bar - The driver sets the size of the access by writing 1, 2 or 4 to cap.length - The driver sets the offset within the BAR by writing to cap.offset At that point, pci_cfg_data will provide a window of size cap.length into the given cap.bar at offset cap.offset. Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Reviewed-by: Hao Li <hao.l.li@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> Acked-by: Kevin Tian <kevin.tian@intel.com>