mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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b5b22bf98b
While the terms to refer to CPU topology levels are originally borrowed from MSR listings in SDMs (i.e. thread, core, die and package), we now align the topology information with the CPUID topology enumeration leaf (which does not have a "package" level) in the implementation. However, some hard-coded level types are not updated accordingly, leading to strangely organized nodes in the generated board XML. This patch refines the CPU extractor of the board inspector by removing such hard code. Also the XPATH counting the total number of threads is refined to tolerate the variance of reported intermediate levels. Tracked-On: #6689 Signed-off-by: Junjie Mao <junjie.mao@intel.com>
81 lines
3.3 KiB
XML
81 lines
3.3 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<!-- Copyright (C) 2021 Intel Corporation. -->
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<!-- SPDX-License-Identifier: BSD-3-Clause -->
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<xsl:stylesheet
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version="1.0"
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xmlns:xi="http://www.w3.org/2003/XInclude"
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xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
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xmlns:dyn="http://exslt.org/dynamic"
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xmlns:math="http://exslt.org/math"
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xmlns:acrn="http://projectacrn.org">
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<xsl:include href="lib.xsl" />
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<xsl:output method="text" />
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<xsl:template match="/acrn-offline-data">
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<!-- Declaration of license -->
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<xsl:value-of select="$license" />
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<!-- Header include guard -->
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<xsl:value-of select="acrn:include-guard('BOARD_INFO_H')" />
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<xsl:apply-templates select="config-data/acrn-config" />
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<xsl:apply-templates select="board-data/acrn-config" />
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<xsl:apply-templates select="allocation-data/acrn-config" />
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<xsl:value-of select="acrn:include-guard-end('BOARD_INFO_H')" />
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</xsl:template>
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<xsl:template match="config-data/acrn-config">
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<xsl:if test="count(//p2sb[text() = 'y'])">
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<xsl:call-template name="p2sb" />
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</xsl:if>
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<xsl:call-template name="MAX_HIDDEN_PDEVS_NUM" />
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</xsl:template>
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<xsl:template match="board-data/acrn-config">
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<xsl:call-template name="MAX_PCPU_NUM" />
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<xsl:call-template name="MAX_VMSIX_ON_MSI_PDEVS_NUM" />
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<xsl:variable name="physical_address_bits" select="//processors/model/attribute[@id='physical_address_bits']/text()" />
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<xsl:if test="$physical_address_bits">
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<xsl:value-of select="acrn:define('MAXIMUM_PA_WIDTH', $physical_address_bits[1], 'U')" />
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</xsl:if>
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</xsl:template>
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<xsl:template match="allocation-data/acrn-config">
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<xsl:apply-templates select="hv/MMIO" />
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</xsl:template>
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<xsl:template name="p2sb">
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<xsl:value-of select="acrn:define('P2SB_VGPIO_DM_ENABLED', '', '')" />
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<xsl:value-of select="acrn:define('P2SB_BAR_ADDR', '0xFD000000', 'UL')" />
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<xsl:value-of select="acrn:define('P2SB_BAR_ADDR_GPA', '0xFD000000', 'UL')" />
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<xsl:value-of select="acrn:define('P2SB_BAR_SIZE', '0x1000000', 'UL')" />
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<xsl:value-of select="acrn:define('P2SB_BASE_GPIO_PORT_ID', '0x69', 'U')" />
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<xsl:value-of select="acrn:define('P2SB_MAX_GPIO_COMMUNITIES', '0x6', 'U')" />
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</xsl:template>
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<xsl:template name="MAX_HIDDEN_PDEVS_NUM">
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<xsl:value-of select="acrn:define('MAX_HIDDEN_PDEVS_NUM', acrn:get-hidden-device-num(), 'U')" />
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</xsl:template>
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<xsl:template name="MAX_PCPU_NUM">
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<xsl:value-of select="acrn:define('MAX_PCPU_NUM', count(//processors//thread), 'U')" />
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</xsl:template>
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<xsl:template name="MAX_VMSIX_ON_MSI_PDEVS_NUM">
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<xsl:value-of select="acrn:define('MAX_VMSIX_ON_MSI_PDEVS_NUM', sum(dyn:map(//device, 'acrn:is-vmsix-supported-device(./vendor, ./identifier)')), 'U')" />
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</xsl:template>
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<xsl:template match="MMIO">
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<xsl:value-of select="acrn:define('MMIO32_START', //MMIO32_START, 'UL')" />
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<xsl:value-of select="acrn:define('MMIO32_END', //MMIO32_END, 'UL')" />
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<xsl:value-of select="acrn:define('MMIO64_START', //MMIO64_START, 'UL')" />
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<xsl:value-of select="acrn:define('MMIO64_END', //MMIO64_END, 'UL')" />
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<xsl:value-of select="acrn:define('HI_MMIO_START', //HI_MMIO_START, 'UL')" />
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<xsl:value-of select="acrn:define('HI_MMIO_END', //HI_MMIO_END, 'UL')" />
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</xsl:template>
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</xsl:stylesheet>
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