Files
acrn-hypervisor/hypervisor/arch/riscv/trap.h
Haicheng Li cf5860f369 risc-v: handle timer interrupt
This patch addes the codes to handle timer interrupt.

Tracked-On: #8792
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-09-17 08:55:12 +08:00

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C

/*
* Copyright (C) 2023-2024 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Authors:
* Haicheng Li <haicheng.li@intel.com>
*/
#ifndef __RISCV_TRAP_H__
#define __RISCV_TRAP_H__
typedef void (* irq_handler_t)(void);
#endif