Files
acrn-hypervisor/hypervisor/arch/x86/cpu.c
Yonghua Huang 34a6336525 HV: enable L1 cache flush when VM entry
- flush L1 cache before VM entry only on platform
   affected by L1TF
 - flush operation is configurable by below MACRO:
    --CONFIG_L1D_FLUSH_VMENTRY_ENABLED

Tracked-On: #1672
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-11-01 11:21:15 +08:00

22 KiB