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064be1e3e6
When all vCPU threads on one pCPU are put to sleep (e.g., when all
guests execute HLT), hv would schedule to idle thread. Currently the
idle thread executes PAUSE which does not enter any c-state and consumes
a lot of power. This patch is to support HLT in the idle thread.
When we switch to HLT, we have to make sure events that would wake a
vCPU must also be able to wake the pCPU. Those events are either
generated by local interrupt or issued by other pCPUs followed by an
ipi kick.
Each of them have an interrupt involved, so they are also able to wake
the halted pCPU. Except when the pCPU has just scheduled to idle thread
but not yet halted, interrupts could be missed.
sleep-------schedule to idle------IRQ ON---HLT--(kick missed)
^
wake---kick|
This areas should be protected. This is done by a safe halt
mechanism leveraging STI instruction’s delay effect (same as Linux).
vCPUs with lapic_pt or hv with CONFIG_KEEP_IRQ_DISABLED=y does not allow
interrupts in root mode, so they could never wake from HLT (INIT kick
does not wake HLT in root mode either). They should continue using PAUSE
in idle.
Tracked-On: #8507
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
88 lines
2.4 KiB
C
88 lines
2.4 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PER_CPU_H
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#define PER_CPU_H
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#include <types.h>
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#include <sbuf.h>
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#include <irq.h>
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#include <timer.h>
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#include <profiling.h>
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#include <logmsg.h>
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#include <schedule.h>
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#include <asm/notify.h>
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#include <asm/page.h>
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#include <asm/gdt.h>
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#include <asm/security.h>
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#include <asm/vm_config.h>
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struct per_cpu_region {
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/* vmxon_region MUST be 4KB-aligned */
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uint8_t vmxon_region[PAGE_SIZE];
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void *vmcs_run;
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#ifdef HV_DEBUG
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struct shared_buf *sbuf[ACRN_SBUF_PER_PCPU_ID_MAX];
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char logbuf[LOG_MESSAGE_MAX_SIZE];
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uint32_t npk_log_ref;
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#endif
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uint64_t irq_count[NR_IRQS];
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uint64_t softirq_pending;
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uint64_t spurious;
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struct acrn_vcpu *ever_run_vcpu;
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#ifdef STACK_PROTECTOR
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struct stack_canary stk_canary;
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#endif
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struct per_cpu_timers cpu_timers;
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struct sched_control sched_ctl;
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struct sched_noop_control sched_noop_ctl;
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struct sched_iorr_control sched_iorr_ctl;
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struct sched_bvt_control sched_bvt_ctl;
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struct sched_prio_control sched_prio_ctl;
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struct thread_object idle;
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struct host_gdt gdt;
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struct tss_64 tss;
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enum pcpu_boot_state boot_state;
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uint64_t pcpu_flag;
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uint8_t mc_stack[CONFIG_STACK_SIZE] __aligned(16);
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uint8_t df_stack[CONFIG_STACK_SIZE] __aligned(16);
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uint8_t sf_stack[CONFIG_STACK_SIZE] __aligned(16);
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uint8_t stack[CONFIG_STACK_SIZE] __aligned(16);
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uint32_t lapic_id;
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uint32_t lapic_ldr;
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uint32_t softirq_servicing;
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uint32_t mode_to_kick_pcpu;
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uint32_t mode_to_idle;
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struct smp_call_info_data smp_call_info;
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struct list_head softirq_dev_entry_list;
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#ifdef PROFILING_ON
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struct profiling_info_wrapper profiling_info;
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#endif
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uint64_t shutdown_vm_bitmap;
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uint64_t tsc_suspend;
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struct acrn_vcpu *whose_iwkey;
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/*
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* We maintain a per-pCPU array of vCPUs. vCPUs of a VM won't
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* share same pCPU. So the maximum possible # of vCPUs that can
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* run on a pCPU is CONFIG_MAX_VM_NUM.
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* vcpu_array address must be aligned to 64-bit for atomic access
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* to avoid contention between offline_vcpu and posted interrupt handler
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*/
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struct acrn_vcpu *vcpu_array[CONFIG_MAX_VM_NUM] __aligned(8);
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} __aligned(PAGE_SIZE); /* per_cpu_region size aligned with PAGE_SIZE */
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extern struct per_cpu_region per_cpu_data[MAX_PCPU_NUM];
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/*
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* get percpu data for pcpu_id.
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*/
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#define per_cpu(name, pcpu_id) \
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(per_cpu_data[(pcpu_id)].name)
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/* get percpu data for current pcpu */
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#define get_cpu_var(name) per_cpu(name, get_pcpu_id())
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#endif
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