mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-03 22:17:03 +00:00
eb8bcb06b3
Modified the copyright year range in code, and corrected "int32_tel" into "Intel" in two "hypervisor/include/debug/profiling.h" and "hypervisor/include/debug/profiling_internal.h". Tracked-On: #7559 Signed-off-by: Ziheng Li <ziheng.li@intel.com>
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* Copyright (C) 2020-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RDT_H
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#define RDT_H
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enum {
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RDT_RESOURCE_L3,
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RDT_RESOURCE_L2,
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RDT_RESOURCE_MBA,
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/* Must be the last */
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RDT_NUM_RESOURCES,
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};
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#define RDT_RESID_L3 1U
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#define RDT_RESID_L2 2U
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#define RDT_RESID_MBA 3U
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extern const uint16_t hv_clos;
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/* The instance of one RES_ID */
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struct rdt_ins {
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union {
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struct {
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uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way
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may be used by other entities in the platform (e.g. GPU) */
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uint16_t cbm_len; /* Length of Cache mask in bits */
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bool is_cdp_enabled; /* True if support CDP */
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} cache;
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struct rdt_membw {
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uint16_t mba_max; /* Max MBA delay throttling value supported */
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bool delay_linear; /* True if memory B/W delay is in linear scale */
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} membw;
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} res;
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uint16_t num_closids; /* Number of CLOSIDs available, 0 indicates resource is not supported.*/
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uint32_t num_clos_config; /* Number of element in clos_config_array */
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union clos_config *clos_config_array;
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uint64_t cpu_mask; /* the CPUs this RDT applies */
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};
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/* The intel Resource Director Tech(RDT) based Allocation Tech support */
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struct rdt_type {
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uint32_t res_id; /* RDT_RESID_L3/RDT_RESID_L2/RDT_RESID_MBA */
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uint32_t msr_qos_cfg; /* MSR addr to IA32_L3/L2_QOS_CFG */
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uint32_t msr_base; /* MSR base to program clos value */
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uint32_t num_ins; /* Number of element in ins_array */
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struct rdt_ins *ins_array;
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};
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void setup_clos(uint16_t pcpu_id);
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uint64_t clos2pqr_msr(uint16_t clos);
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bool is_platform_rdt_capable(void);
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const struct rdt_ins *get_rdt_res_ins(int res, uint16_t pcpu_id);
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#endif /* RDT_H */
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