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For platform that supports RRSBA (Restricted Return Stack Buffer Alternate), using retpoline may not be sufficient to guard against branch history injection or intra-mode branch target injection. RRSBA must be disabled to prevent CPUs from using alternate predictors for RETs. Quoting Intel CVE-2022-0001/CVE-2022-0002: Where software is using retpoline as a mitigation for BHI or intra-mode BTI, and the processor both enumerates RRSBA and enumerates RRSBA_DIS controls, it should disable this behavior. ... Software using retpoline as a mitigation for BHI or intra-mode BTI should use these new indirect predictor controls to disable alternate predictors for RETs. See: https://www.intel.com/content/www/us/en/developer/articles/technical/ software-security-guidance/technical-documentation/branch-history-injection.html Tracked-On: #7907 Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
40 lines
813 B
C
40 lines
813 B
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SECURITY_H
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#define SECURITY_H
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/* type of speculation control
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* 0 - no speculation control support
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* 1 - raw IBRS + IBPB support
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* 2 - with STIBP optimization support
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*/
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#define IBRS_NONE 0
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#define IBRS_RAW 1
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#define IBRS_OPT 2
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#ifndef ASSEMBLER
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int32_t get_ibrs_type(void);
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void cpu_l1d_flush(void);
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bool check_cpu_security_cap(void);
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void cpu_internal_buffers_clear(void);
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bool is_ept_force_4k_ipage(void);
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uint64_t get_random_value(void);
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void disable_rrsba(void);
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#ifdef STACK_PROTECTOR
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struct stack_canary {
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/* Gcc generates extra code, using [fs:40] to access canary */
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uint8_t reserved[40];
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uint64_t canary;
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};
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void set_fs_base(void);
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#endif
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#endif /* ASSEMBLER */
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#endif /* SECURITY_H */
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