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MISRA-C requires that each parameter in the MACRO shall be in brackets. In some cases, adding brackets for all of the parameters may not be a perfect solution. For example, it may affect the code readability when there are many parameters used in the MACRO. And duplicated brackets will appear when one MACRO called another MACRO which is using same parameters. This patch convert some MACROs to inline functions to avoid such cases. v1 -> v2: * Remove the unnecessary changes in hypervisor/bsp/uefi/efi/boot.h Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#include <schedule.h>
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#include <softirq.h>
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static void run_vcpu_pre_work(struct vcpu *vcpu)
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{
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uint64_t *pending_pre_work = &vcpu->pending_pre_work;
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if (bitmap_test_and_clear_lock(ACRN_VCPU_MMIO_COMPLETE, pending_pre_work)) {
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dm_emulate_mmio_post(vcpu);
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}
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}
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void vcpu_thread(struct vcpu *vcpu)
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{
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uint64_t vmexit_begin = 0UL, vmexit_end = 0UL;
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uint32_t basic_exit_reason = 0U;
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uint64_t tsc_aux_hyp_cpu = (uint64_t) vcpu->pcpu_id;
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int32_t ret = 0;
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/* If vcpu is not launched, we need to do init_vmcs first */
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if (!vcpu->launched) {
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init_vmcs(vcpu);
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}
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run_vcpu_pre_work(vcpu);
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do {
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/* handle pending softirq when irq enable*/
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do_softirq();
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CPU_IRQ_DISABLE();
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/* handle risk softirq when disabling irq*/
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do_softirq();
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/* Check and process pending requests(including interrupt) */
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ret = acrn_handle_pending_request(vcpu);
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if (ret < 0) {
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pr_fatal("vcpu handling pending request fail");
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pause_vcpu(vcpu, VCPU_ZOMBIE);
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continue;
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}
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if (need_reschedule(vcpu->pcpu_id) != 0) {
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/*
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* In extrem case, schedule() could return. Which
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* means the vcpu resume happens before schedule()
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* triggered by vcpu suspend. In this case, we need
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* to do pre work and continue vcpu loop after
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* schedule() is return.
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*/
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schedule();
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run_vcpu_pre_work(vcpu);
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continue;
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}
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#ifdef HV_DEBUG
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vmexit_end = rdtsc();
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if (vmexit_begin != 0UL) {
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per_cpu(vmexit_time, vcpu->pcpu_id)[basic_exit_reason]
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+= (vmexit_end - vmexit_begin);
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}
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#endif
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TRACE_2L(TRACE_VM_ENTER, 0UL, 0UL);
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/* Restore guest TSC_AUX */
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if (vcpu->launched) {
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cpu_msr_write(MSR_IA32_TSC_AUX,
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vcpu->msr_tsc_aux_guest);
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}
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ret = start_vcpu(vcpu);
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if (ret != 0) {
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pr_fatal("vcpu resume failed");
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pause_vcpu(vcpu, VCPU_ZOMBIE);
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continue;
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}
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#ifdef HV_DEBUG
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vmexit_begin = rdtsc();
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#endif
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vcpu->arch_vcpu.nrexits++;
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/* Save guest TSC_AUX */
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cpu_msr_read(MSR_IA32_TSC_AUX, &vcpu->msr_tsc_aux_guest);
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/* Restore native TSC_AUX */
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cpu_msr_write(MSR_IA32_TSC_AUX, tsc_aux_hyp_cpu);
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CPU_IRQ_ENABLE();
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/* Dispatch handler */
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ret = vmexit_handler(vcpu);
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basic_exit_reason = vcpu->arch_vcpu.exit_reason & 0xFFFFU;
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if (ret < 0) {
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pr_fatal("dispatch VM exit handler failed for reason"
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" %d, ret = %d!", basic_exit_reason, ret);
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vcpu_inject_gp(vcpu, 0U);
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continue;
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}
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#ifdef HV_DEBUG
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per_cpu(vmexit_cnt, vcpu->pcpu_id)[basic_exit_reason]++;
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#endif
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TRACE_2L(TRACE_VM_EXIT, basic_exit_reason, vcpu_get_rip(vcpu));
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} while (1);
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}
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#ifdef HV_DEBUG
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void get_vmexit_profile(char *str_arg, int str_max)
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{
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char *str = str_arg;
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uint16_t cpu, i;
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int len, size = str_max;
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len = snprintf(str, size, "\r\nNow(us) = %16lld\r\n",
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ticks_to_us(rdtsc()));
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size -= len;
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str += len;
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len = snprintf(str, size, "\r\nREASON");
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size -= len;
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str += len;
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for (cpu = 0U; cpu < phys_cpu_num; cpu++) {
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len = snprintf(str, size, "\t CPU%hu\t US", cpu);
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size -= len;
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str += len;
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}
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for (i = 0U; i < 64U; i++) {
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len = snprintf(str, size, "\r\n0x%x", i);
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size -= len;
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str += len;
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for (cpu = 0U; cpu < phys_cpu_num; cpu++) {
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len = snprintf(str, size, "\t%10lld\t%10lld",
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per_cpu(vmexit_cnt, cpu)[i],
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ticks_to_us(per_cpu(vmexit_time, cpu)[i]));
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size -= len;
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str += len;
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}
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}
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snprintf(str, size, "\r\n");
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}
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#endif /* HV_DEBUG */
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