mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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f65a87585b
1. "make clean && make BOARD=nuc11tnbi5 SCENARIO=shared" will generate the acrn debian package. 2. "make clean && make board_inspector" will generate the acrn board_inspector debian package Tracked-On: #6688 Signed-off-by: Hu Fenglin <fenglin.hu@intel.com>
91 lines
2.5 KiB
Python
91 lines
2.5 KiB
Python
# Copyright (C) 2021 Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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import ctypes
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import copy
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import inspectorlib.cdata as cdata
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class ExtendedCapability:
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# Capability names from PCI Express Base Specification, mostly Table 9-23
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_cap_names_ = {
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0x01: "Advanced Error Reporting",
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0x02: "Virtual Channel",
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0x03: "Device Serial Number",
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0x04: "Power Budgeting",
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0x05: "Root Complex Link Declaration",
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0x06: "Root Complex Internal Link Control",
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0x07: "Root Complex Event Collector Endpoint Association",
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0x08: "Multi-Function Virtual Channel",
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0x09: "Virtual Channel",
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0x0a: "RCRB Header",
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0x0b: "Vendor-Specific Extended",
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0x0c: "Configuration Access Correlation",
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0x0d: "ACS",
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0x0e: "ARI",
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0x0f: "ATS",
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0x10: "SR-IOV",
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0x11: "MR-IOV",
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0x12: "Multicast",
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0x13: "PRI",
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0x15: "Resizable BAR",
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0x16: "DPA",
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0x17: "TPH Requester",
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0x18: "LTR",
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0x19: "Secondary PCI Express",
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0x1a: "PMUX",
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0x1b: "PASID",
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0x1c: "LNR",
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0x1d: "DPC",
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0x1e: "L1 PM Substates",
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0x1f: "TPM",
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0x20: "M-PCIe",
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0x21: "FRS Queueing",
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0x22: "Readiness Time Reporting",
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0x23: "Designated Vendor-Specific",
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0x24: "VF Resizable BAR",
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0x25: "Data Link Feature",
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0x26: "Physical Layer 16.0 GT/s",
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0x27: "Lane Margining at the Receiver",
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0x28: "Hierarchy ID",
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0x29: "NPEM",
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0x2a: "Physical Layer 32.0 GT/s",
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0x2b: "Alternate Protocol",
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0x2c: "SFI",
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}
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@property
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def name(self):
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if self.id in self._cap_names_.keys():
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return self._cap_names_[self.id]
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else:
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return f"Reserved Extended ({hex(self.id)})"
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class ExtendedCapabilityListRegister(cdata.Struct, ExtendedCapability):
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_pack_ = 1
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_fields_ = [
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('id', ctypes.c_uint32, 16),
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('version', ctypes.c_uint32, 4),
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('next_cap_ptr_raw', ctypes.c_uint32, 12),
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]
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@property
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def next_cap_ptr(self):
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return self.next_cap_ptr_raw & 0xffc
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# Module API
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def extended_capabilities(data):
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buf = ctypes.create_string_buffer(data, len(data))
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cap_ptr = 0x100
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acc = list()
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while cap_ptr != 0:
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caplist = ExtendedCapabilityListRegister.from_buffer_copy(buf, cap_ptr)
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if caplist.id != 0:
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acc.append(caplist)
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cap_ptr = caplist.next_cap_ptr
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return acc
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