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cdfc82f03b
- write_vmsix_cap_reg(): emulates vmsix cap writes.
write_pt_vmsix_cap_reg(): emulates msix cap write
for PT devices.
- rw_vmsix_table(): emulates vmsix table bar space access.
- vmsix_handle_table_mmio_access(): emulates the vmsix
bar space access only.
- pt_vmsix_handle_table_mmio_access(): emulates the vmsix
bar space access and remap msi entry for PT device if
write operation is executed.
- rename 'init_vmsix()' and 'deinit_vmsix()' to
'init_vmsix_pt()' and 'deinit_vmsix_pt()' respectively,
they're for PT devices only.
- remove below 2 functions,call
'pci_vdev_read_vcfg()' directly in cases they're used.
- 'read_vmsi_cap_reg()'
- 'read_vmsix_cap_reg()'
Tracked-On: #5407
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Done <eddie.dong@intel.com>
112 lines
3.6 KiB
C
112 lines
3.6 KiB
C
/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <vm.h>
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#include <errno.h>
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#include <vpci.h>
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#include <ept.h>
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#include <mmu.h>
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#include <logmsg.h>
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#include "vpci_priv.h"
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/**
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* @brief Writing MSI-X Capability Structure
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*
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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bool write_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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static const uint8_t msix_ro_mask[12U] = {
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0xffU, 0xffU, 0xffU, 0x3fU, /* Only Function Mask and MSI-X Enable writable */
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0xffU, 0xffU, 0xffU, 0xffU,
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0xffU, 0xffU, 0xffU, 0xffU };
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bool is_written = false;
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uint32_t old, ro_mask = ~0U;
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(void)memcpy_s((void *)&ro_mask, bytes, (void *)&msix_ro_mask[offset - vdev->msix.capoff], bytes);
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if (ro_mask != ~0U) {
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old = pci_vdev_read_vcfg(vdev, offset, bytes);
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pci_vdev_write_vcfg(vdev, offset, bytes, (old & ro_mask) | (val & ~ro_mask));
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is_written = true;
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}
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return is_written;
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}
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/**
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* @pre vdev != NULL
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* @pre io_req != NULL
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* @pre mmio->address >= vdev->msix.mmio_gpa
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*/
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uint32_t rw_vmsix_table(struct pci_vdev *vdev, struct io_request *io_req)
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{
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struct mmio_request *mmio = &io_req->reqs.mmio;
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struct msix_table_entry *entry;
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uint32_t entry_offset, table_offset, index = CONFIG_MAX_MSIX_TABLE_NUM;
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uint64_t offset;
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/* Must be full DWORD or full QWORD aligned. */
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if ((mmio->size == 4U) || (mmio->size == 8U)) {
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offset = mmio->address - vdev->msix.mmio_gpa;
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if (msixtable_access(vdev, (uint32_t)offset)) {
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table_offset = (uint32_t)(offset - vdev->msix.table_offset);
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index = table_offset / MSIX_TABLE_ENTRY_SIZE;
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entry = &vdev->msix.table_entries[index];
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entry_offset = table_offset % MSIX_TABLE_ENTRY_SIZE;
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if (mmio->direction == REQUEST_READ) {
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(void)memcpy_s(&mmio->value, (size_t)mmio->size,
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(void *)entry + entry_offset, (size_t)mmio->size);
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} else {
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(void)memcpy_s((void *)entry + entry_offset, (size_t)mmio->size,
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&mmio->value, (size_t)mmio->size);
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}
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} else if (mmio->direction == REQUEST_READ) {
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mmio->value = 0UL;
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}
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} else {
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pr_err("%s, Only DWORD and QWORD are permitted", __func__);
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}
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return index;
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}
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/**
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* @pre io_req != NULL
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* @pre priv_data != NULL
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*/
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int32_t vmsix_handle_table_mmio_access(struct io_request *io_req, void *priv_data)
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{
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(void)rw_vmsix_table((struct pci_vdev *)priv_data, io_req);
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return 0;
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}
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