Li Fei1 ce3451827a hv: vpci: add vmsix capability registers rw permission control ... Guest may write a MSI-X capability register with only RW bits setting on. This works well on native since the hardware will make sure RO register bits could not over-write. However, the software needs more efforts to achieve this. This patch does this by defining a RW permission mapping base on bits. When a guest tries to write a MSI-X Capability register, only modify the RW bits on vCFG space. Tracked-On: #4550 Signed-off-by: Li Fei1 <fei1.li@intel.com>		2020-05-28 13:44:18 +08:00
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vpci	hv: vpci: add vmsix capability registers rw permission control	2020-05-28 13:44:18 +08:00
io_req.c	hv: mmio: refine mmio access handle lock granularity	2020-02-24 16:17:38 +08:00
vioapic.c	hv: vioapic: minor refine about vioapic_init	2020-04-24 15:35:38 +08:00
vpic.c	hv: vpic: remove vm structure pointer from vpic	2020-03-31 10:57:47 +08:00
vrtc.c	hv: remove 'flags' field in struct vm_io_range	2019-08-19 10:19:54 +08:00
vuart.c	hv: Introduce Global System Interrupt (GSI) into INTx Remapping	2020-03-25 09:36:18 +08:00