Zide Chen d0df39cbb5 hv: emulate CR0.CD and CR0.NW ... This patch makes use of IA32_PAT MSR to emulate cache disabled behaviour When the guest is requesting to set CR0.CD: - Keep guest's CR0.CD and CR0.NW bits unchanged - Write IA32_PAT MSR with all-UC entries to change the effective memory type for all GPA to UC for the guest VCPU - It depends on trapping wrmsr to IA32_PAT to prevent any entry in IA32_PAT being changed to non UC type by the guest When the guest is requesting to clear CR0.CD: - restore the content of guest's IA32_PAT MSR Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2018-07-02 12:33:06 +08:00
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x86	hv: emulate CR0.CD and CR0.NW	2018-07-02 12:33:06 +08:00