Xiangyang Wu d16d0f00bc HV: update destination shorthand during x2apic ICR emulation ... Currently, in RTVM with multi vCPUs, lapic pass through is configured, each vCPU works in x2apic mode. When one vCPU sends IPI to all other vCPUs through writes ICR register with virtual value 0x00000000000c00f8, this ICR writting will be intercepted, the hypervisor passes destination shorthand field 11B (All Excluding Self) in the virtual ICR value into physical ICR value during IPI emulation, this IPI will be sent to each physical CPU core in the platform according to 10.6.1 Interrupt Command Register (ICR), Vol 3, SDM. One vCPU in User VM with lapic pass through configuration can send IPI with destination shorthand (10B or 11B) and any vector (such as NMI or reboot vector) to other vCPUs, this IPI will sent other VMs in the platform by hypervisor, this interference may cause other VMs hang. In this patch, set "Destination Shorthand" field of the ICR value as 00B (No Shorthand) since the emulation is done through sending IPI to each VCPU in dmask one by one. Tracked-On: #6908 Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Chen, Jason CJ <jason.cj.chen@intel.com>		2021-12-01 09:54:35 +08:00
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x86	HV: update destination shorthand during x2apic ICR emulation	2021-12-01 09:54:35 +08:00