mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-11-13 17:34:12 +00:00
0d630e8f37
This patch implements the IPI for RISC-V using SBI interface.
There is no common IPI concept abstracted, due to the following reasons:
- RISC-V:
Software delivers an IPI to target CPUs via software interrupts.
The interrupt number is fixed for each privilege mode (e.g.,
Supervisor Software Interrupt = IRQ 1, Machine Software Interrupt = IRQ 3).
The actual purpose of the IPI is indicated by an IPI message type,
which is a software-level concept. When the IPI is received,
the target CPU must check the message type to determine the required action.
- x86:
Software delivers an IPI to target CPUs using a specific vector number.
During CPU initialization, software can assign dedicated vectors for
particular purposes. When the IPI is received, the target CPU could
directly invoke the handler bound to that vector.
Each architecture provides its own IPI implementation, and other SW modules
directly call these arch-specific functions.
------
Notes:
* To ensure RISC-V builds pass, an empty `include/arch/riscv/asm/cpu.h`
is added since `debug/logmsg.h` includes `asm/cpu.h`.
* Implemented IPI functionality using the SBI IPI Extension (EID #0x735049).
Legacy SBI extensions are not supported in ACRN.
----------
Changelog:
* Updated commit message and code comments to state explicitly that
legacy SBI extensions are not supported in ACRN.
* Refined the prototype of sbi_send_ipi() to align with the SBI spec:
From: int64_t sbi_send_ipi(uint64_t mask)
To: int64_t sbi_send_ipi(uint64_t mask, uint64_t mask_base)
In ACRN it is invoked as sbi_send_ipi(dest_mask, 0UL), with mask_base
set to 0UL.
* Renamed send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() respectively.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
16 lines
247 B
C
16 lines
247 B
C
/*
|
|
* Copyright (C) 2023-2025 Intel Corporation.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*
|
|
* Authors:
|
|
* Haicheng Li <haicheng.li@intel.com>
|
|
*/
|
|
|
|
#ifndef RISCV_IRQ_H
|
|
#define RISCV_IRQ_H
|
|
|
|
#define IPI_NOTIFY_CPU 0
|
|
|
|
#endif /* RISCV_IRQ_H */
|