acrn-hypervisor/hypervisor/include/arch/x86/cpu_state_tbl.h
Victor Sun 7647517a15 HV: trap and validate px request
Currently acrn partitions cpus between SOS and UOS, so the default
policy is to allow guest managing CPU px state. However we would
not blindly passthrough perf_ctrl MSR to guest. Instead guest access
is always trapped and validated by acrn hypervisor before forwarding
to pcpu. Doing so leaves room for future power budget control in
hypervisor, e.g. limiting turbo percentage that a cpu can enter.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00

45 lines
1.9 KiB
C

/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
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* * Redistributions of source code must retain the above copyright
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef CPU_STATE_TBL_H
#define CPU_STATE_TBL_H
struct cpu_state_table {
char model_name[64];
uint8_t px_cnt;
struct cpu_px_data *px_data;
};
void load_cpu_state_data(void);
void vm_setup_cpu_state(struct vm *vm);
int validate_pstate(struct vm *vm, uint64_t perf_ctl);
#endif /* CPU_STATE_TBL_H */