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https://github.com/projectacrn/acrn-hypervisor.git
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555a03db99
Currently the Px Cx supported SoCs which listed in cpu_state_tbl.c is limited, and it is not a wise option to build a huge state table data base to support Px/Cx for other SoCs. This patch give a alternative solution that build a board specific cpu state table in board.c which could be auto-generated by offline tool, then the CPU Px/Cx of customer board could be enabled; Hypervisor will search the cpu state table in cpu_state_tbl[] first, if not found then go check board_cpu_state_tbl. If no matched cpu state table is found then Px/Cx will not be supported; Tracked-On: #3477 Signed-off-by: Victor Sun <victor.sun@intel.com>
34 lines
892 B
C
34 lines
892 B
C
/*
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* Copyright (C) <2018> Intel Corporation
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HOST_PM_H
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#define HOST_PM_H
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#include <acrn_common.h>
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#define BIT_SLP_TYPx 10U
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#define BIT_SLP_EN 13U
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#define BIT_WAK_STS 15U
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struct cpu_state_info {
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uint8_t px_cnt; /* count of all Px states */
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const struct cpu_px_data *px_data;
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uint8_t cx_cnt; /* count of all Cx entries */
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const struct cpu_cx_data *cx_data;
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};
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struct cpu_state_table {
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char model_name[64];
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struct cpu_state_info state_info;
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};
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struct pm_s_state_data *get_host_sstate_data(void);
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void host_enter_s3(struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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extern void asm_enter_s3(struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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extern void restore_s3_context(void);
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struct cpu_state_info *get_cpu_pm_state_info(void);
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#endif /* HOST_PM_H */
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