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https://github.com/projectacrn/acrn-hypervisor.git
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d8b754e53a
GPA base of SW SRAM can't be hardcoded as physical address of SW SRAM(HPA), as this HPA may vary on different platform. This patch reserves a dedicated memory slot[GPA: 2G - 8M, 2G) as SW SRAM region. Tracked-On: #5649 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com> Acked-by: Yu Wang <yu1.wang@intel.com>
48 lines
1.0 KiB
C
48 lines
1.0 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RTCT_H
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#define RTCT_H
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#define RTCT_ENTRY_TYPE_PTCD_LIMIT 1U
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#define RTCT_ENTRY_TYPE_PTCM_BINARY 2U
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#define RTCT_ENTRY_TYPE_WRC_L3_MASKS 3U
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#define RTCT_ENTRY_TYPE_GT_L3_MASKS 4U
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#define RTCT_ENTRY_TYPE_PSRAM 5U
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#define RTCT_ENTRY_TYPE_STREAM_DATAPATH 6U
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#define RTCT_ENTRY_TYPE_TIMEAWARE_SUBSYS 7U
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#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
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#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
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struct rtct_entry {
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uint16_t size;
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uint16_t format;
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uint32_t type;
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uint32_t data[64];
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} __packed;
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struct rtct_entry_data_psram {
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uint32_t cache_level;
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uint64_t base;
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uint32_t ways;
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uint32_t size;
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uint32_t apic_id_tbl[64];
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} __packed;
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struct rtct_entry_data_mem_hi_latency {
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uint32_t hierarchy;
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uint32_t clock_cycles;
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uint32_t apic_id_tbl[64];
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} __packed;
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uint64_t get_software_sram_base_hpa(void);
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uint64_t get_software_sram_size(void);
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uint8_t *build_vrtct(struct vmctx *ctx, void *cfg);
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#endif /* RTCT_H */
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