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https://github.com/projectacrn/acrn-hypervisor.git
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bd1e7a46b3
cleanup arch folder, only include some necessary, doesn't include hypervisor.h Tracked-On: #1842 Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com> modified: arch/x86/configs/apl-mrb/pt_dev.c modified: arch/x86/configs/apl-mrb/ve820.c modified: arch/x86/configs/dnv-cb2/pt_dev.c modified: arch/x86/configs/dnv-cb2/ve820.c modified: arch/x86/configs/partition_config.c modified: arch/x86/configs/sharing_config.c modified: arch/x86/cpu.c modified: arch/x86/cpu_state_tbl.c modified: arch/x86/e820.c modified: arch/x86/gdt.c modified: arch/x86/init.c modified: arch/x86/ioapic.c modified: arch/x86/irq.c modified: arch/x86/lapic.c modified: arch/x86/mmu.c modified: arch/x86/notify.c modified: arch/x86/page.c modified: arch/x86/pagetable.c modified: arch/x86/static_checks.c modified: arch/x86/timer.c modified: arch/x86/trampoline.c modified: arch/x86/vmx.c modified: arch/x86/vtd.c modified: boot/include/acpi.h modified: include/arch/x86/e820.h modified: include/arch/x86/ioapic.h
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <gdt.h>
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#include <per_cpu.h>
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static void set_tss_desc(struct tss_64_descriptor *desc,
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uint64_t tss, size_t tss_limit, uint32_t type)
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{
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uint32_t u1, u2, u3;
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uint32_t tss_hi_32 = (uint32_t)(tss >> 32U);
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uint32_t tss_lo_32 = (uint32_t)tss;
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u1 = tss_lo_32 << 16U;
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u2 = tss_lo_32 & 0xFF000000U;
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u3 = (tss_lo_32 & 0x00FF0000U) >> 16U;
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desc->low32_value = u1 | (tss_limit & 0xFFFFU);
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desc->base_addr_63_32 = tss_hi_32;
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desc->high32_value = u2 | (type << 8U) | 0x8000U | u3;
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}
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static inline void load_gdt(struct host_gdt_descriptor *gdtr)
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{
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asm volatile ("lgdt %0" ::"m"(*gdtr));
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}
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void load_gdtr_and_tr(void)
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{
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struct host_gdt *gdt = &get_cpu_var(gdt);
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struct host_gdt_descriptor gdtr;
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struct tss_64 *tss = &get_cpu_var(tss);
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/* first entry is not used */
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gdt->rsvd = 0xAAAAAAAAAAAAAAAAUL;
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/* ring 0 code sel descriptor */
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gdt->code_segment_descriptor = 0x00Af9b000000ffffUL;
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/* ring 0 data sel descriptor */
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gdt->data_segment_descriptor = 0x00cf93000000ffffUL;
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tss->ist1 = (uint64_t)get_cpu_var(mc_stack) + CONFIG_STACK_SIZE;
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tss->ist2 = (uint64_t)get_cpu_var(df_stack) + CONFIG_STACK_SIZE;
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tss->ist3 = (uint64_t)get_cpu_var(sf_stack) + CONFIG_STACK_SIZE;
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tss->ist4 = 0UL;
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/* tss descriptor */
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set_tss_desc(&gdt->host_gdt_tss_descriptors,
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(uint64_t)tss, sizeof(struct tss_64), TSS_AVAIL);
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gdtr.len = sizeof(struct host_gdt) - 1U;
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gdtr.gdt = gdt;
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load_gdt(&gdtr);
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CPU_LTR_EXECUTE(HOST_GDT_RING0_CPU_TSS_SEL);
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}
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