mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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74622d7d29
merge hv_lib.h and hypervisor.h into one file Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
128 lines
4.1 KiB
C
128 lines
4.1 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*_
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* Emulate a PCI Host bridge:
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* Intel Corporation Celeron N3350/Pentium N4200/Atom E3900
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* Series Host Bridge (rev 0b)
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*/
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#include <hypervisor.h>
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#include "pci_priv.h"
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static int vdev_hostbridge_init(struct pci_vdev *vdev)
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{
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/* PCI config space */
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pci_vdev_write_cfg_u16(vdev, PCIR_VENDOR, 0x8086U);
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pci_vdev_write_cfg_u16(vdev, PCIR_DEVICE, 0x5af0U);
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pci_vdev_write_cfg_u8(vdev, PCIR_REVID, 0xbU);
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pci_vdev_write_cfg_u8(vdev, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL
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| PCIM_MFDEV);
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pci_vdev_write_cfg_u8(vdev, PCIR_CLASS, PCIC_BRIDGE);
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pci_vdev_write_cfg_u8(vdev, PCIR_SUBCLASS, PCIS_BRIDGE_HOST);
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pci_vdev_write_cfg_u8(vdev, 0x34U, 0xe0U);
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pci_vdev_write_cfg_u8(vdev, 0x3cU, 0xe0U);
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pci_vdev_write_cfg_u8(vdev, 0x48U, 0x1U);
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pci_vdev_write_cfg_u8(vdev, 0x4aU, 0xd1U);
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pci_vdev_write_cfg_u8(vdev, 0x4bU, 0xfeU);
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pci_vdev_write_cfg_u8(vdev, 0x50U, 0xc1U);
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pci_vdev_write_cfg_u8(vdev, 0x51U, 0x2U);
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pci_vdev_write_cfg_u8(vdev, 0x54U, 0x33U);
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pci_vdev_write_cfg_u8(vdev, 0x58U, 0x7U);
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pci_vdev_write_cfg_u8(vdev, 0x5aU, 0xf0U);
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pci_vdev_write_cfg_u8(vdev, 0x5bU, 0x7fU);
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pci_vdev_write_cfg_u8(vdev, 0x60U, 0x1U);
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pci_vdev_write_cfg_u8(vdev, 0x63U, 0xe0U);
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pci_vdev_write_cfg_u8(vdev, 0xabU, 0x80U);
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pci_vdev_write_cfg_u8(vdev, 0xacU, 0x2U);
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pci_vdev_write_cfg_u8(vdev, 0xb0U, 0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xb3U, 0x7cU);
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pci_vdev_write_cfg_u8(vdev, 0xb4U, 0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xb6U, 0x80U);
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pci_vdev_write_cfg_u8(vdev, 0xb7U, 0x7bU);
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pci_vdev_write_cfg_u8(vdev, 0xb8U, 0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xbbU, 0x7bU);
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pci_vdev_write_cfg_u8(vdev, 0xbcU, 0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xbfU, 0x80U);
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pci_vdev_write_cfg_u8(vdev, 0xe0U, 0x9U);
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pci_vdev_write_cfg_u8(vdev, 0xe2U, 0xcU);
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pci_vdev_write_cfg_u8(vdev, 0xe3U, 0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xf5U, 0xfU);
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pci_vdev_write_cfg_u8(vdev, 0xf6U, 0x1cU);
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pci_vdev_write_cfg_u8(vdev, 0xf7U, 0x1U);
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return 0;
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}
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static int vdev_hostbridge_deinit(__unused struct pci_vdev *vdev)
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{
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return 0;
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}
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static int vdev_hostbridge_cfgread(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1U)) != 0U) {
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*val = 0xFFFFFFFFU;
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return -EINVAL;
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}
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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return 0;
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}
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static int vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1U)) != 0U) {
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return -EINVAL;
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}
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if (!pci_bar_access(offset)) {
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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}
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return 0;
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}
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struct pci_vdev_ops pci_ops_vdev_hostbridge = {
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.init = vdev_hostbridge_init,
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.deinit = vdev_hostbridge_deinit,
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.cfgread = vdev_hostbridge_cfgread,
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.cfgwrite = vdev_hostbridge_cfgwrite,
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};
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