mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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38d5df723d
to enable APICv Posted interrupt supported, following the specifications defined in Intel SDM Section #29.6, Volume3. Posted-interrupt processing is a feature by which a processor processes the virtual interrupts by recording them as pending on the virtual-APIC page. Injecting interrupts to VCPU from remote CPU without causing VM exit on the destination, following steps in SDM Section 29.6,volume3: Tracked-On: #1447 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
195 lines
6.6 KiB
C
195 lines
6.6 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef VLAPIC_H
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#define VLAPIC_H
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/*
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* 16 priority levels with at most one vector injected per level.
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*/
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#define ISRVEC_STK_SIZE (16U + 1U)
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#define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI
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struct vlapic_pir_desc {
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uint64_t pir[4];
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uint64_t pending;
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uint64_t unused[3];
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} __aligned(64);
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struct vlapic_timer {
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struct hv_timer timer;
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uint32_t mode;
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uint32_t tmicr;
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uint32_t divisor_shift;
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};
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struct acrn_vlapic {
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/*
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* Please keep 'apic_page' and 'pir_desc' be the first two fields in
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* current structure, as below alignment restrictions are mandatory
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* to support APICv features:
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* - 'apic_page' MUST be 4KB aligned.
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* - 'pir_desc' MUST be 64 bytes aligned.
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*/
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struct lapic_regs apic_page;
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struct vlapic_pir_desc pir_desc;
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struct vm *vm;
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struct vcpu *vcpu;
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uint32_t esr_pending;
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int esr_firing;
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struct vlapic_timer vtimer;
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/*
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* The 'isrvec_stk' is a stack of vectors injected by the local apic.
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* A vector is popped from the stack when the processor does an EOI.
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* The vector on the top of the stack is used to compute the
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* Processor Priority in conjunction with the TPR.
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*
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* Note: isrvec_stk_top is unsigned and always equal to the number of
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* vectors in the stack.
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*
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* Operations:
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* init: isrvec_stk_top = 0;
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* push: isrvec_stk_top++; isrvec_stk[isrvec_stk_top] = x;
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* pop : isrvec_stk_top--;
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*/
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uint8_t isrvec_stk[ISRVEC_STK_SIZE];
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uint32_t isrvec_stk_top;
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uint64_t msr_apicbase;
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/*
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* Copies of some registers in the virtual APIC page. We do this for
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* a couple of different reasons:
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* - to be able to detect what changed (e.g. svr_last)
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* - to maintain a coherent snapshot of the register (e.g. lvt_last)
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*/
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uint32_t svr_last;
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uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1];
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} __aligned(CPU_PAGE_SIZE);
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/* APIC write handlers */
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void vlapic_set_cr8(struct acrn_vlapic *vlapic, uint64_t val);
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uint64_t vlapic_get_cr8(struct acrn_vlapic *vlapic);
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/*
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* Returns 0 if there is no eligible vector that can be delivered to the
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* guest at this time and non-zero otherwise.
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*
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* If an eligible vector number is found and 'vecptr' is not NULL then it will
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* be stored in the location pointed to by 'vecptr'.
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*
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* Note that the vector does not automatically transition to the ISR as a
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* result of calling this function.
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*/
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int vlapic_pending_intr(struct acrn_vlapic *vlapic, uint32_t *vecptr);
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/*
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* Transition 'vector' from IRR to ISR. This function is called with the
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* vector returned by 'vlapic_pending_intr()' when the guest is able to
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* accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
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* block interrupt delivery).
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*/
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void vlapic_intr_accepted(struct acrn_vlapic *vlapic, uint32_t vector);
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void vlapic_post_intr(uint16_t dest_pcpu_id);
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uint64_t apicv_get_pir_desc_paddr(struct vcpu *vcpu);
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struct acrn_vlapic *vm_lapic_from_pcpuid(struct vm *vm, uint16_t pcpu_id);
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int vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval);
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int vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t wval);
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/*
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* Signals to the LAPIC that an interrupt at 'vector' needs to be generated
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* to the 'cpu', the state is recorded in IRR.
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*/
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int vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool level);
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#define LAPIC_TRIG_LEVEL true
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#define LAPIC_TRIG_EDGE false
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static inline int
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vlapic_intr_level(struct vcpu *vcpu, uint32_t vector)
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{
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return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_LEVEL);
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}
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static inline int
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vlapic_intr_edge(struct vcpu *vcpu, uint32_t vector)
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{
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return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_EDGE);
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}
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/*
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* Triggers the LAPIC local interrupt (LVT) 'vector' on 'cpu'. 'cpu' can
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* be set to -1 to trigger the interrupt on all CPUs.
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*/
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int vlapic_set_local_intr(struct vm *vm, uint16_t vcpu_id_arg, uint32_t vector);
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int vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg);
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void vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest,
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bool phys, uint32_t delmode, uint32_t vec, bool rh);
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/* Reset the trigger-mode bits for all vectors to be edge-triggered */
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void vlapic_reset_tmr(struct acrn_vlapic *vlapic);
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/*
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* Set the trigger-mode bit associated with 'vector' to level-triggered if
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* the (dest,phys,delmode) tuple resolves to an interrupt being delivered to
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* this 'vlapic'.
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*/
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void vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
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uint32_t vector, bool level);
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void vlapic_apicv_batch_set_tmr(struct acrn_vlapic *vlapic);
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uint32_t vlapic_get_id(struct acrn_vlapic *vlapic);
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uint8_t vlapic_get_apicid(struct acrn_vlapic *vlapic);
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int vlapic_create(struct vcpu *vcpu);
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/*
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* @pre vcpu != NULL
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*/
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void vlapic_free(struct vcpu *vcpu);
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void vlapic_init(struct acrn_vlapic *vlapic);
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void vlapic_reset(struct acrn_vlapic *vlapic);
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void vlapic_restore(struct acrn_vlapic *vlapic, struct lapic_regs *regs);
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bool vlapic_enabled(struct acrn_vlapic *vlapic);
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uint64_t vlapic_apicv_get_apic_access_addr(void);
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uint64_t vlapic_apicv_get_apic_page_addr(struct acrn_vlapic *vlapic);
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void vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic);
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int apic_access_vmexit_handler(struct vcpu *vcpu);
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int apic_write_vmexit_handler(struct vcpu *vcpu);
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int veoi_vmexit_handler(struct vcpu *vcpu);
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int tpr_below_threshold_vmexit_handler(__unused struct vcpu *vcpu);
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void calcvdest(struct vm *vm, uint64_t *dmask, uint32_t dest, bool phys);
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#endif /* VLAPIC_H */
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