mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-08 08:26:55 +00:00
daf495bfc8
This patch parsees physical RTCT entries and dump information about pseudo RAM into the board XML files. A macro named PRE_RTVM_SW_SRAM_BASE_GPA is added to the generated misc_cfg.h according to recent design changes. This patch still writes the board XML file manually, following the convention of the current framework. Using XML-based approach requires a complete refinement of the current generation process as the root `acrn-config` node has its own text among adjacent children. Tracked-On: #5649 Signed-off-by: Junjie Mao <junjie.mao@intel.com>
406 lines
15 KiB
Python
406 lines
15 KiB
Python
# Copyright (C) 2019 Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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import common
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import lxml.etree
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import board_cfg_lib
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import scenario_cfg_lib
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MISC_CFG_HEADER = """#ifndef MISC_CFG_H
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#define MISC_CFG_H"""
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MISC_CFG_END = """#endif /* MISC_CFG_H */"""
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class Vuart:
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t_vm_id = {}
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t_vuart_id = {}
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v_type = {}
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v_base = {}
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v_irq = {}
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def sos_bootarg_diff(sos_cmdlines, config):
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if sos_cmdlines:
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sos_len = len(sos_cmdlines)
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i = 0
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for sos_cmdline in sos_cmdlines:
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if not sos_cmdline:
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continue
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i += 1
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if i == 1:
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if sos_len == 1:
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print('#define SOS_BOOTARGS_DIFF\t"{}"'.format(sos_cmdline.strip('"')), file=config)
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else:
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print('#define SOS_BOOTARGS_DIFF\t"{} " \\'.format(sos_cmdline), file=config)
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else:
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if i < sos_len:
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print('\t\t\t\t"{} "\t\\'.format(sos_cmdline), file=config)
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else:
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print('\t\t\t\t"{}"'.format(sos_cmdline), file=config)
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def parse_boot_info():
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err_dic = {}
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if 'SOS_VM' in common.VM_TYPES.values():
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sos_cmdlines = list(common.get_leaf_tag_map(common.SCENARIO_INFO_FILE, "board_private", "bootargs").values())
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sos_rootfs = list(common.get_leaf_tag_map(common.SCENARIO_INFO_FILE, "board_private", "rootfs").values())
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(err_dic, vuart0_dic, vuart1_dic) = scenario_cfg_lib.get_sos_vuart_settings(launch_flag=False)
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else:
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sos_cmdlines = list(common.get_leaf_tag_map(common.SCENARIO_INFO_FILE, "os_config", "bootargs").values())
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sos_rootfs = list(common.get_leaf_tag_map(common.SCENARIO_INFO_FILE, "os_config", "rootfs").values())
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(err_dic, vuart0_dic, vuart1_dic) = scenario_cfg_lib.get_sos_vuart_settings(launch_flag=False)
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return (err_dic, sos_cmdlines, sos_rootfs, vuart0_dic, vuart1_dic)
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def clos_per_vm_gen(config):
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clos_per_vm = {}
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clos_per_vm = common.get_leaf_tag_map(
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common.SCENARIO_INFO_FILE, "clos", "vcpu_clos")
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for i,clos_list_i in clos_per_vm.items():
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clos_config = scenario_cfg_lib.clos_assignment(clos_per_vm, i)
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print("#define VM{0}_VCPU_CLOS\t\t\t{1}".format(i, clos_config['clos_map']), file=config)
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def cpu_affinity_output(cpu_bits, i, config):
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if "SOS_VM" == common.VM_TYPES[i]:
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print("", file=config)
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print("#define SOS_VM_CONFIG_CPU_AFFINITY\t{0}".format(
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cpu_bits['cpu_map']), file=config)
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else:
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print("#define VM{0}_CONFIG_CPU_AFFINITY\t{1}".format(
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i, cpu_bits['cpu_map']), file=config)
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def cpu_affinity_per_vm_gen(config):
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cpus_per_vm = common.get_leaf_tag_map(
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common.SCENARIO_INFO_FILE, "cpu_affinity", "pcpu_id")
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for vm_i,_ in common.VM_TYPES.items():
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cpu_bits = scenario_cfg_lib.cpus_assignment(cpus_per_vm, vm_i)
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cpu_affinity_output(cpu_bits, vm_i, config)
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print("", file=config)
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def pci_dev_num_per_vm_gen(config):
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pci_items = common.get_leaf_tag_map(common.SCENARIO_INFO_FILE, "pci_devs", "pci_dev")
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pci_devs = scenario_cfg_lib.get_pt_pci_devs(pci_items)
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pt_pci_num = scenario_cfg_lib.get_pt_pci_num(pci_devs)
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ivshmem_region = common.get_hv_item_tag(common.SCENARIO_INFO_FILE,
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"FEATURES", "IVSHMEM", "IVSHMEM_REGION")
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shmem_enabled = common.get_hv_item_tag(common.SCENARIO_INFO_FILE,
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"FEATURES", "IVSHMEM", "IVSHMEM_ENABLED")
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shmem_regions = scenario_cfg_lib.get_shmem_regions(ivshmem_region)
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shmem_num = scenario_cfg_lib.get_shmem_num(shmem_regions)
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vuarts = common.get_vuart_info(common.SCENARIO_INFO_FILE)
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pci_vuarts_num = scenario_cfg_lib.get_pci_vuart_num(vuarts)
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for vm_i,vm_type in common.VM_TYPES.items():
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num = 0
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if "POST_LAUNCHED_VM" == scenario_cfg_lib.VM_DB[vm_type]['load_type']:
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shmem_num_i = 0
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pci_vuart_num = pci_vuarts_num[vm_i]
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if shmem_enabled == 'y' and vm_i in shmem_num.keys():
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shmem_num_i = shmem_num[vm_i]
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num = shmem_num_i + pci_vuart_num
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elif "PRE_LAUNCHED_VM" == scenario_cfg_lib.VM_DB[vm_type]['load_type']:
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shmem_num_i = 0
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if shmem_enabled == 'y' and vm_i in shmem_num.keys():
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shmem_num_i = shmem_num[vm_i]
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num = pt_pci_num[vm_i] + shmem_num_i + pci_vuarts_num[vm_i]
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if pt_pci_num[vm_i] > 0 or shmem_num_i > 0 or pci_vuarts_num[vm_i] > 0:
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# if there is passthrough device or ivshmem, vhostbridge is needed
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num += 1
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elif "SOS_VM" == scenario_cfg_lib.VM_DB[vm_type]['load_type']:
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continue
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if num > 0:
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print("#define VM{}_CONFIG_PCI_DEV_NUM\t{}U".format(vm_i, num), file=config)
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print("", file=config)
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def split_cmdline(cmd_str, config):
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cmd_list = [i for i in cmd_str.strip('"').split()]
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if not cmd_list: return
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last_idx = len(cmd_list) - 1
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for idx, cmd_arg in enumerate(cmd_list):
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if idx == 0:
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print('"', end="", file=config)
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elif idx % 4 == 0:
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print("\\\n", end="", file=config)
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if idx == last_idx:
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print('{}"'.format(cmd_arg), file=config)
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else:
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print('{} '.format(cmd_arg), end="", file=config)
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def boot_args_per_vm_gen(config):
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kern_args = common.get_leaf_tag_map(common.SCENARIO_INFO_FILE, "os_config", "bootargs")
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for vm_i,vm_type in common.VM_TYPES.items():
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if "PRE_LAUNCHED_VM" == scenario_cfg_lib.VM_DB[vm_type]['load_type']:
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if vm_i in kern_args.keys() and kern_args[vm_i]:
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print("#define VM{}_BOOT_ARGS\t".format(vm_i), end="", file=config)
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split_cmdline(kern_args[vm_i].strip(), config)
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print("", file=config)
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print("", file=config)
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def pt_intx_num_vm0_gen(config):
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phys_gsi, virt_gsi = common.get_pt_intx_table(common.SCENARIO_INFO_FILE)
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if (board_cfg_lib.is_matched_board(("ehl-crb-b"))
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and phys_gsi.get(0) is not None
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and len(phys_gsi[0]) > 0):
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print("#define VM0_PT_INTX_NUM\t{}U".format(len(phys_gsi[0])), file=config)
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else:
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print("#define VM0_PT_INTX_NUM\t0U", file=config)
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print("", file=config)
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def swsram_base_gpa_gen(config):
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board_etree = lxml.etree.parse(common.BOARD_INFO_FILE)
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bases = board_etree.xpath("//RTCT/SoftwareSRAM/base")
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if bases:
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min_base = min(map(lambda x: int(x.text, 16), bases))
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print("#define PRE_RTVM_SW_SRAM_BASE_GPA\t{}UL".format(hex(min_base)), file=config)
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print("", file=config)
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def generate_file(config):
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"""
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Start to generate board.c
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:param config: it is a file pointer of board information for writing to
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"""
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board_cfg_lib.get_valid_irq(common.BOARD_INFO_FILE)
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# get the vuart0/vuart1 which user chosed from scenario.xml of board_private section
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(err_dic, ttys_n) = board_cfg_lib.parser_hv_console()
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if err_dic:
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return err_dic
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# parse sos_bootargs/rootfs/console
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(err_dic, sos_cmdlines, sos_rootfs, vuart0_dic, vuart1_dic) = parse_boot_info()
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if err_dic:
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return err_dic
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if vuart0_dic:
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# parse to get poart/base of vuart0/vuart1
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vuart0_port_base = board_cfg_lib.LEGACY_TTYS[list(vuart0_dic.keys())[0]]
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vuart0_irq = vuart0_dic[list(vuart0_dic.keys())[0]]
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vuart1_port_base = board_cfg_lib.LEGACY_TTYS[list(vuart1_dic.keys())[0]]
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vuart1_irq = vuart1_dic[list(vuart1_dic.keys())[0]]
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# parse the setting ttys vuatx dic: {vmid:base/irq}
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vuart0_setting = Vuart()
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vuart1_setting = Vuart()
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vuart0_setting = common.get_vuart_info_id(common.SCENARIO_INFO_FILE, 0)
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vuart1_setting = common.get_vuart_info_id(common.SCENARIO_INFO_FILE, 1)
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# sos command lines information
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sos_cmdlines = [i for i in sos_cmdlines[0].split() if i != '']
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# add maxcpus parameter into sos cmdlines if there are pre-launched VMs
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pcpu_list = board_cfg_lib.get_processor_info()
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cpu_affinity = common.get_leaf_tag_map(common.SCENARIO_INFO_FILE, "cpu_affinity", "pcpu_id")
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pre_cpu_list = []
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sos_cpu_num = 0
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for vmid, cpu_list in cpu_affinity.items():
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if vmid in common.VM_TYPES and cpu_list != [None]:
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vm_type = common.VM_TYPES[vmid]
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load_type = ''
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if vm_type in scenario_cfg_lib.VM_DB:
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load_type = scenario_cfg_lib.VM_DB[vm_type]['load_type']
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if load_type == "PRE_LAUNCHED_VM":
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pre_cpu_list += cpu_list
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elif load_type == "SOS_VM":
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sos_cpu_num += len(cpu_list)
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if sos_cpu_num == 0:
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sos_cpu_num_max = len(list(set(pcpu_list) - set(pre_cpu_list)))
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else:
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sos_cpu_num_max = sos_cpu_num
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if sos_cpu_num_max > 0:
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sos_cmdlines.append('maxcpus='+str(sos_cpu_num_max))
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# get native rootfs list from board_info.xml
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(root_devs, root_dev_num) = board_cfg_lib.get_rootfs(common.BOARD_INFO_FILE)
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# start to generate misc_cfg.h
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print("{0}".format(board_cfg_lib.HEADER_LICENSE), file=config)
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print("{}".format(MISC_CFG_HEADER), file=config)
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print("", file=config)
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# define rootfs with macro
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#for i in range(root_dev_num):
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# print('#define ROOTFS_{}\t\t"root={} "'.format(i, root_devs[i]), file=config)
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# sos rootfs and console
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if "SOS_VM" in common.VM_TYPES.values():
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print('#define SOS_ROOTFS\t\t"root={} "'.format(sos_rootfs[0]), file=config)
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if ttys_n:
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print('#define SOS_CONSOLE\t\t"console={} "'.format(ttys_n), file=config)
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else:
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print('#define SOS_CONSOLE\t\t" "', file=config)
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# sos com base/irq
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i_type = 0
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for vm_i,vm_type in common.VM_TYPES.items():
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if vm_type == "SOS_VM":
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i_type = vm_i
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break
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if "SOS_VM" in common.VM_TYPES.values():
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if vuart0_dic:
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print("#define SOS_COM1_BASE\t\t{}U".format(vuart0_port_base), file=config)
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print("#define SOS_COM1_IRQ\t\t{}U".format(vuart0_irq), file=config)
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else:
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print("#define SOS_COM1_BASE\t\t0U", file=config)
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print("#define SOS_COM1_IRQ\t\t0U", file=config)
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if vuart1_setting[i_type]['base'] != "INVALID_COM_BASE":
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print("#define SOS_COM2_BASE\t\t{}U".format(vuart1_port_base), file=config)
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print("#define SOS_COM2_IRQ\t\t{}U".format(vuart1_irq), file=config)
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# sos boot command line
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print("", file=config)
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if "SOS_VM" in common.VM_TYPES.values():
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sos_bootarg_diff(sos_cmdlines, config)
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print("", file=config)
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cpu_affinity_per_vm_gen(config)
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common_clos_max = board_cfg_lib.get_common_clos_max()
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max_mba_clos_entries = common_clos_max
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max_cache_clos_entries = common_clos_max
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comments_max_clos = '''
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/*
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* The maximum CLOS that is allowed by ACRN hypervisor,
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* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
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* among all supported RDT resources in the platform. In other words, it is
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* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
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* CLOS allocations between all the RDT resources.
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*/'''
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comments_max_mba_clos = '''
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/*
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* Max number of Cache Mask entries corresponding to each CLOS.
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* This can vary if CDP is enabled vs disabled, as each CLOS entry
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* will have corresponding cache mask values for Data and Code when
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* CDP is enabled.
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*/'''
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comments_max_cache_clos = '''
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/* Max number of MBA delay entries corresponding to each CLOS. */'''
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if board_cfg_lib.is_cdp_enabled():
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max_cache_clos_entries_cdp_enable = 2 * common_clos_max
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(res_info, rdt_res_clos_max, clos_max_mask_list) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE)
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common_clos_max_cdp_disable = min(rdt_res_clos_max)
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print("#ifdef CONFIG_RDT_ENABLED", file=config)
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print("#ifdef CONFIG_CDP_ENABLED", file=config)
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print(comments_max_clos, file=config)
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print("#define HV_SUPPORTED_MAX_CLOS\t{}U".format(common_clos_max), file=config)
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print(comments_max_cache_clos, file=config)
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print("#define MAX_CACHE_CLOS_NUM_ENTRIES\t{}U".format(max_cache_clos_entries_cdp_enable), file=config)
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print("#else", file=config)
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print(comments_max_clos, file=config)
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print("#define HV_SUPPORTED_MAX_CLOS\t{}U".format(common_clos_max_cdp_disable), file=config)
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print(comments_max_cache_clos, file=config)
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print("#define MAX_CACHE_CLOS_NUM_ENTRIES\t{}U".format(max_cache_clos_entries), file=config)
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print("#endif", file=config)
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print(comments_max_mba_clos, file=config)
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print("#define MAX_MBA_CLOS_NUM_ENTRIES\t{}U".format(max_mba_clos_entries), file=config)
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else:
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print("#ifdef CONFIG_RDT_ENABLED", file=config)
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print(comments_max_clos, file=config)
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print("#define HV_SUPPORTED_MAX_CLOS\t{}U".format(common_clos_max), file=config)
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print(comments_max_mba_clos, file=config)
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print("#define MAX_MBA_CLOS_NUM_ENTRIES\t{}U".format(max_mba_clos_entries), file=config)
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print(comments_max_cache_clos, file=config)
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print("#define MAX_CACHE_CLOS_NUM_ENTRIES\t{}U".format(max_cache_clos_entries), file=config)
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if not board_cfg_lib.is_rdt_supported():
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print("#endif", file=config)
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print("", file=config)
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if board_cfg_lib.is_rdt_supported():
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(rdt_resources, rdt_res_clos_max, _) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE)
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cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK")
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mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY")
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idx = 0
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for mba_delay_mask in mba_delay_list:
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print("#define MBA_MASK_{}\t\t\t{}U".format(idx, mba_delay_mask), file=config)
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idx += 1
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idx = 0
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for cat_mask in cat_mask_list:
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print("#define CLOS_MASK_{}\t\t\t{}U".format(idx, cat_mask), file=config)
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idx += 1
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print("", file=config)
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clos_per_vm_gen(config)
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print("#endif", file=config)
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print("", file=config)
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vm0_pre_launch = False
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common.get_vm_types()
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for vm_idx,vm_type in common.VM_TYPES.items():
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if vm_idx == 0 and scenario_cfg_lib.VM_DB[vm_type]['load_type'] == "PRE_LAUNCHED_VM":
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vm0_pre_launch = True
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if vm0_pre_launch and board_cfg_lib.is_tpm_passthru():
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tpm2_passthru_enabled = common.get_leaf_tag_map_bool(common.SCENARIO_INFO_FILE, "mmio_resources", "TPM2")
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if 0 in tpm2_passthru_enabled and tpm2_passthru_enabled[0]:
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print("#define VM0_PASSTHROUGH_TPM", file=config)
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print("#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL", file=config)
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gpa = common.hpa2gpa(0, 0xFED40000, 0x5000)
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print("#define VM0_TPM_BUFFER_BASE_ADDR_GPA 0x{:X}UL".format(gpa), file=config)
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print("#define VM0_TPM_BUFFER_SIZE 0x5000UL", file=config)
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print("", file=config)
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pci_dev_num_per_vm_gen(config)
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|
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boot_args_per_vm_gen(config)
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pt_intx_num_vm0_gen(config)
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|
|
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swsram_base_gpa_gen(config)
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|
|
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print("{}".format(MISC_CFG_END), file=config)
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|
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return err_dic
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