Li, Fei1 dbe3d986c0 hv: lapic: save lapic base MSR when suspend ...

Although the lapic base MSR have the same value in per-cpu except that the BSP bit.
However, we would enter s3 on the BSP cpu. After the resume from s3, the BSP bit was
clear on the BSP cpu. This patch fix this bug.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

2018-11-22 12:44:21 +08:00

..

x86

hv: lapic: save lapic base MSR when suspend

2018-11-22 12:44:21 +08:00