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https://github.com/projectacrn/acrn-hypervisor.git
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8b16be9185
Many of the license and Intel copyright headers include the "All rights reserved" string. It is not relevant in the context of the BSD-3-Clause license that the code is released under. This patch removes those strings throughout the code (hypervisor, devicemodel and misc). Tracked-On: #7254 Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
309 lines
8.2 KiB
C
309 lines
8.2 KiB
C
/*-
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* Copyright (c) 2017 Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "vmmapi.h"
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#include "sw_load.h"
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#include "dm.h"
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#include "pci_core.h"
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#include "vssram.h"
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int with_bootargs;
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static char bootargs[BOOT_ARG_LEN];
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/*
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* Default e820 mem map:
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*
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* there is reserved memory hole for PCI hole and APIC etc
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* so the memory layout could be separated into lowmem & highmem.
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* - if request memory size <= ctx->lowmem_limit, then there is only
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* map[0]:0~ctx->lowmem for RAM
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* ctx->lowmem = request_memory_size
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* - if request memory size > ctx->lowmem_limit, then there are
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* map[0]:0~ctx->lowmem_limit & map[2]:4G~ctx->highmem for RAM
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* ctx->highmem = request_memory_size - ctx->lowmem_limit
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*
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* Begin Limit Type Length
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* 0: 0 - 0xA0000 RAM 0xA0000
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* 1: 0x100000 - lowmem part1 RAM 0x0
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* 2: SW SRAM_bot - SW SRAM_top (reserved) VSSRAM_MAX_SIZE
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* 3: gpu_rsvd_bot - gpu_rsvd_top (reserved) 0x4004000
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* 4: lowmem part2 - 0x80000000 (reserved) 0x0
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* 5: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
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* 6: HIGHRAM_START_ADDR - mmio64 start RAM ctx->highmem
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*
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* FIXME: Do we need to reserve DSM and OPREGION for GVTD here.
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*/
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const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
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{ /* 0 to video memory */
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.baseaddr = 0x00000000,
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.length = 0xA0000,
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.type = E820_TYPE_RAM
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},
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{ /* 1MB to lowmem part1 */
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.baseaddr = 1 * MB,
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.length = 0x0,
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.type = E820_TYPE_RAM
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},
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/*
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* VSSRAM area: size: 0x800000
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* In native, the VSSRAM region should be part of DRAM memory.
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* But one fixed VSSRAM gpa is friendly for virtualization due
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* to decoupled with various guest memory size.
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*/
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{
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.baseaddr = 0x0,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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{ /* GPU DSM & OpRegion reserved region */
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.baseaddr = 0x0,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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{ /* lowmem part2 to lowmem_limit */
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.baseaddr = 0x0,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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{ /* ECFG_BASE to 4GB */
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.baseaddr = PCI_EMUL_ECFG_BASE,
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.length = (4 * GB) - PCI_EMUL_ECFG_BASE,
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.type = E820_TYPE_RESERVED
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},
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{ /* 5GB to highmem */
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.baseaddr = HIGHRAM_START_ADDR,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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};
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int
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acrn_parse_bootargs(char *arg)
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{
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size_t len = strnlen(arg, BOOT_ARG_LEN);
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if (len < BOOT_ARG_LEN) {
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strncpy(bootargs, arg, len + 1);
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with_bootargs = 1;
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pr_notice("SW_LOAD: get bootargs %s\n", bootargs);
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return 0;
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}
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return -1;
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}
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char*
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get_bootargs(void)
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{
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return bootargs;
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}
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int
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check_image(char *path, size_t size_limit, size_t *size)
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{
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FILE *fp;
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long len;
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fp = fopen(path, "r");
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if (fp == NULL) {
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pr_err("SW_LOAD ERR: image file failed to open\n");
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return -1;
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}
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fseek(fp, 0, SEEK_END);
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len = ftell(fp);
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if (len == 0 || (size_limit && len > size_limit)) {
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pr_err("SW_LOAD ERR: file is %s\n",
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len ? "too large" : "empty");
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fclose(fp);
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return -1;
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}
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fclose(fp);
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*size = len;
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return 0;
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}
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/* Assumption:
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* the range [start, start + size] belongs to one entry of e820 table
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*/
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int
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add_e820_entry(struct e820_entry *e820, int len, uint64_t start,
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uint64_t size, uint32_t type)
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{
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int i, length = len;
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uint64_t e_s, e_e;
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for (i = 0; i < len; i++) {
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e_s = e820[i].baseaddr;
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e_e = e820[i].baseaddr + e820[i].length;
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if ((e_s <= start) && ((start + size) <= e_e)) {
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int index_s = 0, index_e = 3;
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uint64_t pt[4];
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uint32_t pt_t[3];
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pt[0] = e_s;
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pt[1] = start;
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pt[2] = start + size;
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pt[3] = e_e;
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pt_t[0] = e820[i].type;
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pt_t[1] = type;
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pt_t[2] = e820[i].type;
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if (e_s == start) {
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index_s = 1;
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}
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if (e_e == (start + size)) {
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index_e = 2;
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}
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length += index_e - index_s - 1;
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if ((i != (len - 1) && ((index_e - index_s) > 1))) {
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memmove(&e820[i + index_e - index_s],
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&e820[i + 1], (len - i - 1) *
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sizeof(struct e820_entry));
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}
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for (; index_s < index_e; index_s++, i++) {
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e820[i].baseaddr = pt[index_s];
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e820[i].length = pt[index_s + 1] - pt[index_s];
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e820[i].type = pt_t[index_s];
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}
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break;
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}
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}
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return length;
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}
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uint32_t
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acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820)
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{
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uint32_t removed = 0, k;
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uint32_t gpu_rsvmem_base_gpa = 0;
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uint64_t vssram_gpa = 0;
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memcpy(e820, e820_default_entries, sizeof(e820_default_entries));
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/* FIXME: Here wastes 8MB memory if VSSRAM is enabled, and 64MB+16KB if
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* GPU reserved memory is exist.
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*
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* Determines the GPU region due to DSM identical mapping.
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*/
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gpu_rsvmem_base_gpa = get_gpu_rsvmem_base_gpa();
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if (gpu_rsvmem_base_gpa) {
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e820[LOWRAM_E820_ENTRY + 2].baseaddr = gpu_rsvmem_base_gpa;
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e820[LOWRAM_E820_ENTRY + 2].length = get_gpu_rsvmem_size();
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} else {
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e820[LOWRAM_E820_ENTRY + 2].baseaddr = ctx->lowmem_limit;
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}
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/* Always put VSSRAM before GPU region and keep 1MB boundary for protection. */
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vssram_gpa = get_vssram_gpa_base();
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if (vssram_gpa) {
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e820[LOWRAM_E820_ENTRY + 1].baseaddr = vssram_gpa;
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e820[LOWRAM_E820_ENTRY + 1].length = get_vssram_size();
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} else {
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e820[LOWRAM_E820_ENTRY + 1].baseaddr = e820[LOWRAM_E820_ENTRY + 2].baseaddr;
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}
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if (ctx->lowmem <= e820[LOWRAM_E820_ENTRY + 1].baseaddr) {
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/* Caculation for lowmem part1 */
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e820[LOWRAM_E820_ENTRY].length =
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ctx->lowmem - e820[LOWRAM_E820_ENTRY].baseaddr;
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} else {
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/* Caculation for lowmem part1 */
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e820[LOWRAM_E820_ENTRY].length =
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e820[LOWRAM_E820_ENTRY + 1].baseaddr - e820[LOWRAM_E820_ENTRY].baseaddr;
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/* Caculation for lowmem part2 */
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e820[LOWRAM_E820_ENTRY + 3].baseaddr =
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e820[LOWRAM_E820_ENTRY + 2].baseaddr + e820[LOWRAM_E820_ENTRY + 2].length;
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if (ctx->lowmem > e820[LOWRAM_E820_ENTRY + 3].baseaddr) {
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e820[LOWRAM_E820_ENTRY + 3].length =
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ctx->lowmem - e820[LOWRAM_E820_ENTRY + 3].baseaddr;
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e820[LOWRAM_E820_ENTRY + 3].type = E820_TYPE_RAM;
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}
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}
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/* Caculation for highmem */
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if (ctx->highmem > 0) {
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e820[HIGHRAM_E820_ENTRY].type = E820_TYPE_RAM;
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e820[HIGHRAM_E820_ENTRY].length = ctx->highmem;
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}
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/* Remove empty entries in e820 table */
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for (k = 0; k < (NUM_E820_ENTRIES - 1 - removed); k++) {
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if (e820[k].length == 0x0) {
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memmove(&e820[k], &e820[k + 1], sizeof(struct e820_entry) *
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(NUM_E820_ENTRIES - (k + 1)));
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k--;
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removed++;
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}
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}
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pr_info("SW_LOAD: build e820 %d entries to addr: %p\r\n",
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NUM_E820_ENTRIES - removed, (void *)e820);
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for (k = 0; k < NUM_E820_ENTRIES - removed; k++)
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pr_info("SW_LOAD: entry[%d]: addr 0x%016lx, size 0x%016lx, "
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" type 0x%x\r\n",
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k, e820[k].baseaddr,
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e820[k].length,
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e820[k].type);
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return (NUM_E820_ENTRIES - removed);
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}
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int
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acrn_sw_load(struct vmctx *ctx)
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{
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if (vsbl_file_name)
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return acrn_sw_load_vsbl(ctx);
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else if ((ovmf_file_name != NULL) ^ (ovmf_code_file_name && ovmf_vars_file_name))
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return acrn_sw_load_ovmf(ctx);
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else if (kernel_file_name)
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return acrn_sw_load_bzimage(ctx);
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else if (elf_file_name)
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return acrn_sw_load_elf(ctx);
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else
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return -1;
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}
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