Chenli Wei a1b266f807 misc: refine CLOS module for expansibility ...

This patch refine CLOS module by the following aspects:

1 Unified CACHE_ID type to Hex Format
2 Rewrite policy merge with RDT Class
3 Modify the logic of generate CPU mask

Signed-off-by: Chenli Wei <chenli.wei@intel.com>

2022-05-11 17:00:51 +08:00

..

lib

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00

bdf.py

misc: refine vuart connection

2022-03-08 17:07:48 +08:00

board_capability.py

config-tools: generate ACFG_MAX_PCI_BUS_NUM based on board.xml

2021-12-13 11:06:10 +08:00

clos.py

misc: refine CLOS module for expansibility

2022-05-11 17:00:51 +08:00

cpu_affinity.py

config_tools: track whether each vCPU is used for real-time or not

2022-04-21 10:08:53 +08:00

gpa.py

config-tools: extract the SSRAM area size

2022-04-18 16:47:23 +08:00

guest_flags.py

misc: set PMU_PT flag for pre-launched RTVM

2022-03-29 09:34:17 +08:00

intx.py

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00

main.py

misc: fix the issue of create hv node

2022-04-28 13:42:54 +08:00

memory_allocator.py

config_tools: update the hugepage algorithm

2022-05-07 10:51:10 +08:00

pio.py

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00