mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-18 13:19:44 +00:00
0cd85749fe
Save the native cs limit and reuse it for SOS cs limit. To remove the hardcode of cs limit for guest in hypervisor. Tracked-On: #1231 Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Eddie Dong <Eddie.dong@intel.com>
98 lines
2.7 KiB
ArmAsm
98 lines
2.7 KiB
ArmAsm
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm0_boot.h>
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.section entry, "ax"
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.align 8
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.code32
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.global cpu_primary_save_32
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cpu_primary_save_32:
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/* save context from 32bit mode */
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lea vm0_boot_context, %eax
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sgdt BOOT_CTX_GDT_OFFSET(%eax)
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sidt BOOT_CTX_IDT_OFFSET(%eax)
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str BOOT_CTX_TR_SEL_OFFSET(%eax)
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sldt BOOT_CTX_LDT_SEL_OFFSET(%eax)
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movl %cr0, %ecx
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movl %ecx, BOOT_CTX_CR0_OFFSET(%eax)
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movl %cr3, %ecx
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movl %ecx, BOOT_CTX_CR3_OFFSET(%eax)
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movl %cr4, %ecx
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movl %ecx, BOOT_CTX_CR4_OFFSET(%eax)
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mov %cs, %cx
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mov %cx, BOOT_CTX_CS_SEL_OFFSET(%eax)
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lar %ecx, %ecx
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/* CS AR start from bit 8 */
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shr $8, %ecx
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/* Clear Limit field, bit 8-11 */
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andl $0x0000f0ff, %ecx
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mov %ecx, BOOT_CTX_CS_AR_OFFSET(%eax)
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/* Save CS limit field */
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mov %cs, %cx
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xor %edx, %edx
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lsl %ecx, %edx
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mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%eax)
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mov %es, BOOT_CTX_ES_SEL_OFFSET(%eax)
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mov %ss, BOOT_CTX_SS_SEL_OFFSET(%eax)
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mov %ds, BOOT_CTX_DS_SEL_OFFSET(%eax)
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mov %fs, BOOT_CTX_FS_SEL_OFFSET(%eax)
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mov %gs, BOOT_CTX_GS_SEL_OFFSET(%eax)
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ret
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.code64
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.global cpu_primary_save_64
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cpu_primary_save_64:
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/* save context from 64bit mode */
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lea vm0_boot_context(%rip), %r8
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sgdt BOOT_CTX_GDT_OFFSET(%r8)
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sidt BOOT_CTX_IDT_OFFSET(%r8)
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str BOOT_CTX_TR_SEL_OFFSET(%r8)
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sldt BOOT_CTX_LDT_SEL_OFFSET(%r8)
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mov %cr0, %rcx
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mov %rcx, BOOT_CTX_CR0_OFFSET(%r8)
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mov %cr3, %rcx
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mov %rcx, BOOT_CTX_CR3_OFFSET(%r8)
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mov %cr4, %rcx
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mov %rcx, BOOT_CTX_CR4_OFFSET(%r8)
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mov %cs, %cx
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mov %cx, BOOT_CTX_CS_SEL_OFFSET(%r8)
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lar %ecx, %ecx
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/* CS AR start from bit 8 */
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shr $8, %ecx
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/* Clear Limit field, bit 8-11 */
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andl $0x0000f0ff, %ecx
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mov %ecx, BOOT_CTX_CS_AR_OFFSET(%r8)
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/* Save CS limit field */
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mov %cs, %cx
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xor %edx, %edx
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lsl %ecx, %edx
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mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%r8)
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mov %es, BOOT_CTX_ES_SEL_OFFSET(%r8)
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mov %ss, BOOT_CTX_SS_SEL_OFFSET(%r8)
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mov %ds, BOOT_CTX_DS_SEL_OFFSET(%r8)
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mov %fs, BOOT_CTX_FS_SEL_OFFSET(%r8)
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mov %gs, BOOT_CTX_GS_SEL_OFFSET(%r8)
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/* 0xc0000080 = MSR_IA32_EFER */
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movl $0xc0000080, %ecx
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rdmsr
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movl %eax, BOOT_CTX_EFER_LOW_OFFSET(%r8)
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movl %edx, BOOT_CTX_EFER_HIGH_OFFSET(%r8)
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ret
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.text
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.align 8
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.global vm0_boot_context
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vm0_boot_context:
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.rept SIZE_OF_BOOT_CTX
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.byte 0x00
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.endr
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