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9c5e16987a
Intel SDM Vol3 23.8 says: The INIT signal is blocked whenever a logical processor is in VMX root operation. It is not blocked in VMX nonroot operation. Instead, INITs cause VM exits So, there is no side-effect to send INIT signal regardless of pcpu active status. Tracked-On: #2865 Signed-off-by: Kaige Fu <kaige.fu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef INTR_LAPIC_H
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#define INTR_LAPIC_H
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#include <types.h>
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#include <apicreg.h>
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/* intr_lapic_icr_delivery_mode */
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#define INTR_LAPIC_ICR_FIXED 0x0U
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#define INTR_LAPIC_ICR_LP 0x1U
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#define INTR_LAPIC_ICR_SMI 0x2U
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#define INTR_LAPIC_ICR_NMI 0x4U
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#define INTR_LAPIC_ICR_INIT 0x5U
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#define INTR_LAPIC_ICR_STARTUP 0x6U
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/* intr_lapic_icr_dest_mode */
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#define INTR_LAPIC_ICR_PHYSICAL 0x0U
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#define INTR_LAPIC_ICR_LOGICAL 0x1U
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/* intr_lapic_icr_level */
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#define INTR_LAPIC_ICR_DEASSERT 0x0U
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#define INTR_LAPIC_ICR_ASSERT 0x1U
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/* intr_lapic_icr_trigger */
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#define INTR_LAPIC_ICR_EDGE 0x0U
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#define INTR_LAPIC_ICR_LEVEL 0x1U
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/* intr_lapic_icr_shorthand */
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#define INTR_LAPIC_ICR_USE_DEST_ARRAY 0x0U
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#define INTR_LAPIC_ICR_SELF 0x1U
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#define INTR_LAPIC_ICR_ALL_INC_SELF 0x2U
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#define INTR_LAPIC_ICR_ALL_EX_SELF 0x3U
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/* LAPIC register bit and bitmask definitions */
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#define LAPIC_SVR_VECTOR 0x000000FFU
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#define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100U
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#define LAPIC_LVT_MASK 0x00010000U
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#define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700U
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/* LAPIC Timer bit and bitmask definitions */
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#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0U << 17U)
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#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1U << 17U)
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#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2U << 17U)
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enum intr_cpu_startup_shorthand {
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INTR_CPU_STARTUP_USE_DEST,
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INTR_CPU_STARTUP_ALL_EX_SELF,
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INTR_CPU_STARTUP_UNKNOWN,
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};
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/* x2APIC Interrupt Command Register (ICR) structure */
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union apic_icr {
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uint64_t value;
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struct {
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uint32_t lo_32;
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uint32_t hi_32;
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} value_32;
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struct {
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uint32_t vector:8;
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uint32_t delivery_mode:3;
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uint32_t destination_mode:1;
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uint32_t rsvd_1:2;
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uint32_t level:1;
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uint32_t trigger_mode:1;
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uint32_t rsvd_2:2;
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uint32_t shorthand:2;
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uint32_t rsvd_3:12;
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uint32_t dest_field:32;
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} bits;
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};
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/**
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* @brief Save context of lapic
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*
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* @param[inout] regs Pointer to struct lapic_regs to hold the
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* context of current lapic
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*/
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void save_lapic(struct lapic_regs *regs);
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void early_init_lapic(void);
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void init_lapic(uint16_t pcpu_id);
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void send_lapic_eoi(void);
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/**
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* @brief Get the lapic id
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*
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* @return lapic id
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*/
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uint32_t get_cur_lapic_id(void);
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/**
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* @brief Send an SIPI to a specific cpu
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*
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* Send an Startup IPI to a specific cpu, to notify the cpu to start booting.
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*
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* @param[in] cpu_startup_shorthand The startup_shorthand
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* @param[in] dest_pcpu_id The id of destination physical cpu
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* @param[in] cpu_startup_start_address The address for the dest pCPU to start running
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*
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* @pre cpu_startup_shorthand < INTR_CPU_STARTUP_UNKNOWN
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*/
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void send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
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uint16_t dest_pcpu_id,
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uint64_t cpu_startup_start_address);
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/**
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* @brief Send an IPI to multiple pCPUs
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*
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* @param[in] dest_mask The mask of destination physical cpus
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* @param[in] vector The vector of interrupt
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*/
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void send_dest_ipi_mask(uint32_t dest_mask, uint32_t vector);
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/**
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* @brief Send an IPI to a single pCPU
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*
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* @param[in] pcpu_id The id of destination physical cpu
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* @param[in] vector The vector of interrupt
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*/
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void send_single_ipi(uint16_t pcpu_id, uint32_t vector);
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/**
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* @brief Send an INIT signal to a single pCPU
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*
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* @param[in] pcpu_id The id of destination physical cpu
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*
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* @return None
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*/
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void send_single_init(uint16_t pcpu_id);
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void suspend_lapic(void);
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void resume_lapic(void);
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#endif /* INTR_LAPIC_H */
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