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e793b5d091
The current implement will cache each ISR vector in ISR vector stack and do ISR vector stack check when updating PPR. However, there is no need to do this because: 1) We will not touch vlapic->isrvec_stk[0] except doing vlapic_reset: So we don't need to do vlapic->isrvec_stk[0] check. 2) We only deliver higher priority interrupt from IRR to ISR: So we don't need to check whether vlapic->isrvec_stk interrupts is always increasing. 3) There're only 15 different priority interrupt, It will not happened that more that 15 interrupts could been delivered to ISR: So we don't need to check whether vlapic->isrvec_stk_top will larger than ISRVEC_STK_SIZE which is 16. This patch try to remove ISR vector stack and use isrv to cache the vector number for the highest priority bit that is set in the ISR. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com>
ACRN Hypervisor ############### The open source `Project ACRN`_ defines a device hypervisor reference stack and an architecture for running multiple software subsystems, managed securely, on a consolidated system by means of a virtual machine manager. It also defines a reference framework implementation for virtual device emulation, called the "ACRN Device Model". The ACRN Hypervisor is a Type 1 reference hypervisor stack, running directly on the bare-metal hardware, and is suitable for a variety of IoT and embedded device solutions. The ACRN hypervisor addresses the gap that currently exists between datacenter hypervisors, and hard partitioning hypervisors. The ACRN hypervisor architecture partitions the system into different functional domains, with carefully selected guest OS sharing optimizations for IoT and embedded devices. You can find out more about Project ACRN on the `Project ACRN documentation`_ website. .. _`Project ACRN`: https://projectacrn.org .. _`ACRN Hypervisor`: https://github.com/projectacrn/acrn-hypervisor .. _`Project ACRN documentation`: https://projectacrn.github.io/