Sainath Grandhi e9fe6efd81 hv: vLAPIC ICR write and destination mask matching for x2APIC ...

When guest uses vLAPIC in x2APIC mode, ICR write is a single MSR write.
Also, the destination field for device interrupts and IPIs should not be
handled in the same way as xAPIC mode. This patch adds support for x2APIC
mode operation of guest vLAPIC.

Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>

2018-11-02 13:48:43 +08:00

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x86

hv: vLAPIC ICR write and destination mask matching for x2APIC

2018-11-02 13:48:43 +08:00