yuhong.tao@intel.com ea1bce0cbf HV: enumerate capability of #AC for Splitlock Access ... When the destination of an atomic memory operation located in 2 cache lines, it is called a Splitlock Access. LOCK# bus signal is asserted for splitlock access which may lead to long latency. #AC for Splitlock Access is a CPU feature, it allows rise alignment check exception #AC(0) instead of asserting LOCK#, that is helpful to detect Splitlock Access. This feature is enumerated by MSR(0xcf) IA32_CORE_CAPABILITIES[bit5] Add helper function: bool has_core_cap(uint32_t bitmask) Tracked-On: #4496 Signed-off-by: Tao Yuhong <yuhong.tao@intel.com> Reviewed-by: Yan, Like <like.yan@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2020-04-17 09:53:59 +08:00
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x86	HV: enumerate capability of #AC for Splitlock Access	2020-04-17 09:53:59 +08:00