mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-28 01:53:45 +00:00
4d13ad9d08
- enable NX feature in hypervisor:
1. Set 'XD' bit for all pages, including pages for guests
when initialize MMU tables in hypervisor.
2. remove 'XD' bit for pages that contain hypervisor instructions.
3. enable MSR EFER.NXE,which will enable page access restriction by
preventing instruction fetches form pages with XD bit set.
- remove "-Wl -z noexecstack" GCC flag option in hypervisor
Makefile as it would not affect stack attribute in hyervisor,
which setup stack itself, instead of by loader.
Tracked-On: #1122
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
231 lines
6.7 KiB
ArmAsm
231 lines
6.7 KiB
ArmAsm
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* This is entry for AP startup and BSP S3 wakeup
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*
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* When system jump to trampoline_start16, the CPU is in x86 real
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* mode with no stack setup. CS:IP points to trampoline_start16.
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*
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* The CPU will be changed to long mode finally with temperay
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* page table and gdt in this file. Then jump to different C main
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* entry according to whether it's AP startup or BSP S3 resume.
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* The real page table and gdt will be setup in C main entry.
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*/
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#include <spinlock.h>
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/* NOTE:
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*
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* MISRA C requires that all unsigned constants should have the suffix 'U'
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* (e.g. 0xffU), but the assembler may not accept such C-style constants. For
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* example, binutils 2.26 fails to compile assembly in that case. To work this
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* around, all unsigned constants must be explicitly spells out in assembly
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* with a comment tracking the original expression from which the magic
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* number is calculated. As an example:
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*
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* /* 0x00000668 =
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* * (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) *\/
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* movl $0x00000668, %eax
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*
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* Make sure that these numbers are updated accordingly if the definition of
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* the macros involved are changed.
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*/
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.extern cpu_secondary_init
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.section .trampoline_reset,"ax"
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.align 4
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.code16
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.global trampoline_start16
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.org 0
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trampoline_start16:
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/* Disable local interrupts */
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cli
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/*
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* There are two paths system could come here:
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* - AP startup
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* Silicon will set AP to real mode and setup CS:IP before
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* jmp to trampoline_start16. And the IP is always 0 for sure.
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* - BSP wakeup from S3
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* Some bootloader (like ABL) doesn't guarante IP is set to
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* zero before jump to trampoline_start16 after system resume
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* from S3.
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*
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* To make trampoline code could work with all these cases, a far
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* jump is issued here as fixup. It will update the CS:IP according
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* to where the trampoline code is located.
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*
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* Here, we issue a far jump with "JMP ptr16:16" format (please refer
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* sdm vol2A - JMP instruction description). The jump target is set
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* to trampoline_fixup_target_addr. From trampoline_fixup_target_addr,
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* The CS has same value for both AP startup and BSP wakeup from S3.
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*
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* Because the limitation of real mode (can't access ip register
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* directly. So can't setup the trampoline_fixup_ip and
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* trampoline_fixup_cs), we have to update the trampoline_fixup_ip
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* and trampoline_fixup_cs when we preparing the trampoline code.
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*
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* Refer to preparing_trampoline() for fixup CS:IP setup
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*/
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.byte 0xea /* Opcode of "JMP ptr16:16" */
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.global trampoline_fixup_ip
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trampoline_fixup_ip:
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.word 0 /* "EIP is intruction following JUMP instruction" */
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.global trampoline_fixup_cs
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trampoline_fixup_cs:
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.word 0 /* CS */
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.global trampoline_fixup_target
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trampoline_fixup_target:
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mov %cs, %ax
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mov %ax, %ds
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/* Set DE, PAE, MCE and OS support bits in CR4 */
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/* 0x00000668 =
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* (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) */
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movl $0x00000668, %eax
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mov %eax, %cr4
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/* Set CR3 to PML4 table address */
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movl $cpu_boot_page_tables_ptr, %ebx
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mov (%ebx), %eax
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mov %eax, %cr3
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/* Set LME bit in EFER */
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/* 0xc0000080 = MSR_IA32_EFER */
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movl $0xc0000080, %ecx
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rdmsr
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/* 0x00000100 = MSR_IA32_EFER_LME_BIT */
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orl $0x00000100, %eax
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wrmsr
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/* 0xc0000080 = MSR_IA32_EFER */
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movl $0xc0000080, %ecx
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rdmsr
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/* 0x00000800 = MSR_IA32_EFER_NXE_BIT */
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orl $0x00000800, %eax
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wrmsr
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/* Enable paging, protection, numeric error and co-processor
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monitoring in CR0 to enter long mode */
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mov %cr0, %ebx
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/* 0x80000023 = (CR0_PG | CR0_PE | CR0_MP | CR0_NE) */
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orl $0x80000023, %ebx
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mov %ebx, %cr0
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/* Load temportary GDT pointer value */
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lgdt (trampoline_gdt_ptr - trampoline_start16)
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/* Perform a long jump based to start executing in 64-bit mode */
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movl $trampoline_start64_fixup, %ebx
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ljmpl *(%ebx)
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.align 8
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.global trampoline_start64_fixup
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trampoline_start64_fixup:
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.long trampoline_start64
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/* 0x0008 = HOST_GDT_RING0_CODE_SEL */
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.word 0x0008
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.code64
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trampoline_start64:
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/* Set up all other data segment registers */
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/* 0x0010 = HOST_GDT_RING0_DATA_SEL */
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movl $0x0010, %eax
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mov %eax, %ss
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mov %eax, %ds
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mov %eax, %es
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mov %eax, %fs
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mov %eax, %gs
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/* Obtain CPU spin-lock to serialize trampoline for different APs */
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movq trampoline_spinlock_ptr(%rip), %rdi
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spinlock_obtain(%rdi)
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/* Initialize temporary stack pointer
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NOTE: Using the PML4 memory (PDPT address is top of memory
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for the PML4 page) for the temporary stack
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as we are only using the very first entry in
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this page and the stack is growing down from
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the top of this page. This stack is only
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used for a VERY short period of time, so
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this reuse of PML4 memory should be acceptable. */
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lea trampoline_pdpt_addr(%rip), %rsp
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/* Jump to C entry */
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movq main_entry(%rip), %rax
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jmp *%rax
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/* main entry */
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.align 8
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.global main_entry
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main_entry:
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.quad cpu_secondary_init /* default entry is AP start entry */
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.global trampoline_spinlock_ptr
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trampoline_spinlock_ptr:
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.quad trampoline_spinlock
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/* GDT table */
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.align 4
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trampoline_gdt:
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.quad 0x0000000000000000
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.quad 0x00af9b000000ffff
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.quad 0x00cf93000000ffff
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trampoline_gdt_end:
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/* GDT pointer */
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.align 2
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.global trampoline_gdt_ptr
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trampoline_gdt_ptr:
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.short (trampoline_gdt_end - trampoline_gdt) - 1
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.quad trampoline_gdt
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/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
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.align 4
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.global cpu_boot_page_tables_ptr
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cpu_boot_page_tables_ptr:
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.long cpu_boot_page_tables_start
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/*0x1000 = PAGE_SIZE*/
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.align 0x1000
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.global cpu_boot_page_tables_start
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cpu_boot_page_tables_start:
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/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
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.quad trampoline_pdpt_addr + 0x3
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/*0x1000 = PAGE_SIZE*/
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.align 0x1000
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.global trampoline_pdpt_addr
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trampoline_pdpt_addr:
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address = 0
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.rept 4
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/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
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.quad trampoline_pdt_addr + address + 0x3
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/*0x1000 = PAGE_SIZE*/
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address = address + 0x1000
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.endr
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/*0x1000 = PAGE_SIZE*/
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.align 0x1000
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trampoline_pdt_addr:
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address = 0
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.rept 2048
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/* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
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.quad address + 0x83
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address = address + 0x200000
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.endr
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.end
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