Sainath Grandhi ef03385f42 hv: Write Buffer Flush - VT-d ...

This patch does the following changes
According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers
are flushed implicitly upon Remapping Hardware Caches Invalidation even on
platforms that set RWBF to 1 in capability register. So removed write buffer
flushing as current ACRN issues cache invalidation commands in all cases.

Tracked-On: #1855
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>

2018-12-24 22:18:30 +08:00

..

arch/x86

hv: Write Buffer Flush - VT-d

2018-12-24 22:18:30 +08:00

common

scheduler: make scheduling based on struct sched_object

2018-12-21 10:34:15 +08:00

debug

profiling: split profiling_vmexit_handler into two functions

2018-12-14 08:54:30 +08:00

dm

hv: fix MISRA-C violations "Pointer param should be declared pointer to const."

2018-12-19 13:03:03 +08:00

lib

hv: coding style: refine the remaining functions to one exit point

2018-12-21 19:39:56 +08:00

public

doc: fix vhm_request doxygen comment

2018-12-21 08:50:53 -08:00

hv_debug.h

HV: Added Initial support for SEP/SOCWATCH profiling

2018-10-26 13:39:07 +08:00

hypervisor.h

HV:treewide:rename vm data structure

2018-11-05 15:35:49 +08:00