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https://github.com/projectacrn/acrn-hypervisor.git
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f01aad7e77
ACRN currently uses 2MB large pages in the page tables setup for trampoline code and data. This patch lets ACRN use 1GB large pages instead. When it comes to fixing symbols in trampoline code, fixing pointers in PDPT is no more needed as PDPT PTEs contain Physical Address. Tracked-On: #3899 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <mmu.h>
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#include <per_cpu.h>
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#include <trampoline.h>
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#include <reloc.h>
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#include <vboot.h>
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#include <ld_sym.h>
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static uint64_t trampoline_start16_paddr;
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/*
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* Because trampoline code is relocated in different way, if HV code
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* accesses trampoline using relative addressing, it needs to take
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* out the HV relocation delta
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*
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* This function is valid if:
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* - The hpa of HV code is always higher than trampoline code
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* - The HV code is always relocated to higher address, compared
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* with CONFIG_HV_RAM_START
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*/
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static uint64_t trampoline_relo_addr(const void *addr)
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{
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return (uint64_t)addr - get_hv_image_delta();
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}
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uint64_t read_trampoline_sym(const void *sym)
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{
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uint64_t *hva = (uint64_t *)(hpa2hva(trampoline_start16_paddr) + trampoline_relo_addr(sym));
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return *hva;
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}
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void write_trampoline_sym(const void *sym, uint64_t val)
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{
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uint64_t *hva = (uint64_t *)(hpa2hva(trampoline_start16_paddr) + trampoline_relo_addr(sym));
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*hva = val;
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clflush(hva);
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}
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void write_trampoline_stack_sym(uint16_t pcpu_id)
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{
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uint64_t *hva, stack_sym_addr;
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hva = (uint64_t *)(hpa2hva(trampoline_start16_paddr) + trampoline_relo_addr(secondary_cpu_stack));
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stack_sym_addr = (uint64_t)&per_cpu(stack, pcpu_id)[CONFIG_STACK_SIZE - 1];
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stack_sym_addr &= ~(CPU_STACK_ALIGN - 1UL);
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*hva = stack_sym_addr;
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clflush(hva);
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}
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uint64_t get_trampoline_start16_paddr(void)
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{
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return trampoline_start16_paddr;
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}
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/*
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* @pre pcpu_has_cap(X86_FEATURE_PAGE1GB) == true
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*/
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static void update_trampoline_code_refs(uint64_t dest_pa)
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{
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void *ptr;
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uint64_t val;
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/*
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* calculate the fixup CS:IP according to fixup target address
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* dynamically.
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*
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* trampoline code starts in real mode,
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* so the target addres is HPA
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*/
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val = dest_pa + trampoline_relo_addr(&trampoline_fixup_target);
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_fixup_cs));
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*(uint16_t *)(ptr) = (uint16_t)((val >> 4U) & 0xFFFFU);
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_fixup_ip));
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*(uint16_t *)(ptr) = (uint16_t)(val & 0xfU);
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/* Update temporary page tables */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&cpu_boot_page_tables_ptr));
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*(uint32_t *)(ptr) += (uint32_t)dest_pa;
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&cpu_boot_page_tables_start));
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*(uint64_t *)(ptr) += dest_pa;
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/* update the gdt base pointer with relocated offset */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_gdt_ptr));
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*(uint64_t *)(ptr + 2) += dest_pa;
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/* update trampoline jump pointer with relocated offset */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_start64_fixup));
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*(uint32_t *)ptr += (uint32_t)dest_pa;
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/* update trampoline's main entry pointer */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(main_entry));
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*(uint64_t *)ptr += get_hv_image_delta();
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}
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uint64_t prepare_trampoline(void)
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{
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uint64_t size, dest_pa, i;
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size = (uint64_t)(&ld_trampoline_end - &ld_trampoline_start);
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dest_pa = get_ap_trampoline_buf();
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pr_dbg("trampoline code: %llx size %x", dest_pa, size);
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/* Copy segment for AP initialization code below 1MB */
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(void)memcpy_s(hpa2hva(dest_pa), (size_t)size, &ld_trampoline_load,
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(size_t)size);
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update_trampoline_code_refs(dest_pa);
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for (i = 0UL; i < size; i = i + CACHE_LINE_SIZE) {
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clflush(hpa2hva(dest_pa + i));
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}
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trampoline_start16_paddr = dest_pa;
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return dest_pa;
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}
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