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https://github.com/projectacrn/acrn-hypervisor.git
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5c81659713
EPT tables are shared by MMU and IOMMU. Some IOMMUs don't support page-walk coherency, the cpu cache of EPT entires should be flushed to memory after modifications, so that the modifications are visible to the IOMMUs. This patch adds a new interface to flush the cache of modified EPT entires. There are different implementations for EPT/PPT entries: - For PPT, there is no need to flush the cpu cache after update. - For EPT, need to call iommu_flush_cache to make the modifications visible to IOMMUs. Tracked-On: #3607 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Anthony Xu <anthony.xu@intel.com>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PAGE_H
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#define PAGE_H
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#define PAGE_SHIFT 12U
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#define PAGE_SIZE (1U << PAGE_SHIFT)
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#define PAGE_MASK 0xFFFFFFFFFFFFF000UL
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/* size of the low MMIO address space: 2GB */
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#define PLATFORM_LO_MMIO_SIZE 0x80000000UL
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/* size of the high MMIO address space: 1GB */
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#define PLATFORM_HI_MMIO_SIZE 0x40000000UL
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#define PML4_PAGE_NUM(size) 1UL
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#define PDPT_PAGE_NUM(size) (((size) + PML4E_SIZE - 1UL) >> PML4E_SHIFT)
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#define PD_PAGE_NUM(size) (((size) + PDPTE_SIZE - 1UL) >> PDPTE_SHIFT)
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#define PT_PAGE_NUM(size) (((size) + PDE_SIZE - 1UL) >> PDE_SHIFT)
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/*
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* The size of the guest physical address space, covered by the EPT page table of a VM.
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* With the assumptions:
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* - The GPA of DRAM & MMIO are contiguous.
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* - Guest OS won't re-program device MMIO bars to the address not covered by
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* this EPT_ADDRESS_SPACE.
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*/
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#define EPT_ADDRESS_SPACE(size) (((size) != 0UL) ? ((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE) : 0UL)
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#define TRUSTY_PML4_PAGE_NUM(size) (1UL)
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#define TRUSTY_PDPT_PAGE_NUM(size) (1UL)
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#define TRUSTY_PD_PAGE_NUM(size) (PD_PAGE_NUM(size))
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#define TRUSTY_PT_PAGE_NUM(size) (PT_PAGE_NUM(size))
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#define TRUSTY_PGTABLE_PAGE_NUM(size) \
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(TRUSTY_PML4_PAGE_NUM(size) + TRUSTY_PDPT_PAGE_NUM(size) + TRUSTY_PD_PAGE_NUM(size) + TRUSTY_PT_PAGE_NUM(size))
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struct acrn_vm;
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struct page {
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uint8_t contents[PAGE_SIZE];
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} __aligned(PAGE_SIZE);
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union pgtable_pages_info {
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struct {
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struct page *pml4_base;
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struct page *pdpt_base;
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struct page *pd_base;
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struct page *pt_base;
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} ppt;
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struct {
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uint64_t top_address_space;
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struct page *nworld_pml4_base;
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struct page *nworld_pdpt_base;
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struct page *nworld_pd_base;
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struct page *nworld_pt_base;
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struct page *sworld_pgtable_base;
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struct page *sworld_memory_base;
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} ept;
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};
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struct memory_ops {
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union pgtable_pages_info *info;
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uint64_t (*get_default_access_right)(void);
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uint64_t (*pgentry_present)(uint64_t pte);
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struct page *(*get_pml4_page)(const union pgtable_pages_info *info);
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struct page *(*get_pdpt_page)(const union pgtable_pages_info *info, uint64_t gpa);
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struct page *(*get_pd_page)(const union pgtable_pages_info *info, uint64_t gpa);
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struct page *(*get_pt_page)(const union pgtable_pages_info *info, uint64_t gpa);
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void *(*get_sworld_memory_base)(const union pgtable_pages_info *info);
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void (*clflush_pagewalk)(const void *p);
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};
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extern const struct memory_ops ppt_mem_ops;
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void init_ept_mem_ops(struct acrn_vm *vm);
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void *get_reserve_sworld_memory_base(void);
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#endif /* PAGE_H */
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