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https://github.com/projectacrn/acrn-hypervisor.git
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2fe4280cfa
idx_in: - If the caller of dmar_assign_irte passes a valid IRTE index, it will be resued; - If the caller of dmar_assign_irte passes INVALID_IRTE_ID as IRTE index, the function will allocate a new IRTE. idx_out: This paramter return the actual index of IRTE used. The caller need to check whether the return value is valid or not. Also this patch adds an internal function alloc_irte. The function takes count as input paramter to allocate continuous IRTEs. The count can only be 1, 2, 4, 8, 16 or 32. This is prepared for multiple MSI vector support. Tracked-On: #4831 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
85 lines
4.1 KiB
C
85 lines
4.1 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <util.h>
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#include <boot_context.h>
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#include <acrn_common.h>
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#include <vcpu.h>
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#include <mmu.h>
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#include <trusty.h>
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#define CAT__(A,B) A ## B
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#define CAT_(A,B) CAT__(A,B)
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#define CTASSERT(expr) \
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typedef int32_t CAT_(CTA_DummyType,__LINE__)[(expr) ? 1 : -1]
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/* This is to make sure the 16 bits vpid won't overflow */
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#if ((CONFIG_MAX_VM_NUM * MAX_VCPUS_PER_VM) > 0xffffU)
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#error "VM number or VCPU number are too big"
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#endif
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#if ((CONFIG_HV_RAM_START & (MEM_2M - 1UL)) != 0UL)
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#error "CONFIG_HV_RAM_START must be aligned to 2MB"
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#endif
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#if ((CONFIG_HV_RAM_SIZE & (MEM_2M - 1UL)) != 0UL)
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#error "CONFIG_HV_RAM_SIZE must be integral multiple of 2MB"
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#endif
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#if ((CONFIG_MAX_IR_ENTRIES < 256U) || (CONFIG_MAX_IR_ENTRIES & (CONFIG_MAX_IR_ENTRIES -1)) != 0U)
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#error "CONFIG_MAX_IR_ENTRIES must >=256 and be 2^n"
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#endif
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/* Build time sanity checks to make sure hard-coded offset
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* is matching the actual offset!
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*/
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CTASSERT(BOOT_CTX_CR0_OFFSET == offsetof(struct acrn_vcpu_regs, cr0));
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CTASSERT(BOOT_CTX_CR3_OFFSET == offsetof(struct acrn_vcpu_regs, cr3));
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CTASSERT(BOOT_CTX_CR4_OFFSET == offsetof(struct acrn_vcpu_regs, cr4));
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CTASSERT(BOOT_CTX_IDT_OFFSET == offsetof(struct acrn_vcpu_regs, idt));
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CTASSERT(BOOT_CTX_GDT_OFFSET == offsetof(struct acrn_vcpu_regs, gdt));
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CTASSERT(BOOT_CTX_LDT_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ldt_sel));
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CTASSERT(BOOT_CTX_TR_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, tr_sel));
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CTASSERT(BOOT_CTX_CS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, cs_sel));
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CTASSERT(BOOT_CTX_SS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ss_sel));
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CTASSERT(BOOT_CTX_DS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ds_sel));
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CTASSERT(BOOT_CTX_ES_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, es_sel));
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CTASSERT(BOOT_CTX_FS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, fs_sel));
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CTASSERT(BOOT_CTX_GS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, gs_sel));
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CTASSERT(BOOT_CTX_CS_AR_OFFSET == offsetof(struct acrn_vcpu_regs, cs_ar));
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CTASSERT(BOOT_CTX_EFER_LOW_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer));
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CTASSERT(BOOT_CTX_EFER_HIGH_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer) + 4);
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CTASSERT(CPU_CONTEXT_OFFSET_RAX == offsetof(struct acrn_gp_regs, rax));
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CTASSERT(CPU_CONTEXT_OFFSET_RBX == offsetof(struct acrn_gp_regs, rbx));
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CTASSERT(CPU_CONTEXT_OFFSET_RCX == offsetof(struct acrn_gp_regs, rcx));
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CTASSERT(CPU_CONTEXT_OFFSET_RDX == offsetof(struct acrn_gp_regs, rdx));
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CTASSERT(CPU_CONTEXT_OFFSET_RBP == offsetof(struct acrn_gp_regs, rbp));
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CTASSERT(CPU_CONTEXT_OFFSET_RSI == offsetof(struct acrn_gp_regs, rsi));
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CTASSERT(CPU_CONTEXT_OFFSET_RDI == offsetof(struct acrn_gp_regs, rdi));
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CTASSERT(CPU_CONTEXT_OFFSET_R8 == offsetof(struct acrn_gp_regs, r8));
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CTASSERT(CPU_CONTEXT_OFFSET_R9 == offsetof(struct acrn_gp_regs, r9));
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CTASSERT(CPU_CONTEXT_OFFSET_R10 == offsetof(struct acrn_gp_regs, r10));
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CTASSERT(CPU_CONTEXT_OFFSET_R11 == offsetof(struct acrn_gp_regs, r11));
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CTASSERT(CPU_CONTEXT_OFFSET_R12 == offsetof(struct acrn_gp_regs, r12));
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CTASSERT(CPU_CONTEXT_OFFSET_R13 == offsetof(struct acrn_gp_regs, r13));
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CTASSERT(CPU_CONTEXT_OFFSET_R14 == offsetof(struct acrn_gp_regs, r14));
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CTASSERT(CPU_CONTEXT_OFFSET_R15 == offsetof(struct acrn_gp_regs, r15));
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CTASSERT(CPU_CONTEXT_OFFSET_CR2 == offsetof(struct run_context, cr2));
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CTASSERT(CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL
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== offsetof(struct run_context, ia32_spec_ctrl));
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CTASSERT(CPU_CONTEXT_OFFSET_RFLAGS == offsetof(struct run_context, rflags));
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CTASSERT(CPU_CONTEXT_OFFSET_CR3 - CPU_CONTEXT_OFFSET_EXTCTX_START
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== offsetof(struct ext_context, cr3));
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CTASSERT(CPU_CONTEXT_OFFSET_IDTR - CPU_CONTEXT_OFFSET_EXTCTX_START
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== offsetof(struct ext_context, idtr));
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CTASSERT(CPU_CONTEXT_OFFSET_LDTR - CPU_CONTEXT_OFFSET_EXTCTX_START
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== offsetof(struct ext_context, ldtr));
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CTASSERT((sizeof(struct trusty_startup_param)
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+ sizeof(struct trusty_key_info)) < 0x1000U);
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CTASSERT(NR_WORLD == 2);
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CTASSERT(sizeof(struct vhm_request) == (4096U/VHM_REQUEST_MAX));
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