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f15a3600ec
Fix tsc_deadline issue by trapping TSC_DEADLINE msr write if VMX_TSC_OFFSET is not 0. Because there is an assupmtion in the ACRN vART design that pTSC_Adjust and vTSC_Adjust are both 0. We can leave the TSC_DEADLINE write pass-through without correctness issue becuase there is no offset between the pTSC and vTSC, and there is no write to vTSC or vTSC_Adjust write observed in the RTOS so far. This commit fix the potential correctness issue, but the RT performance will be badly affected if vTSC or vTSC_Adjust was not zero, which we will address if such case happened. Tracked-On: #3636 Signed-off-by: Yan, Like <like.yan@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>