Yan, Like f15cc7d6de hv: set/clear TMR bit like hardware behave ... Current ACRN implementation update TMR bits one time only when related RTE fields changed, which is not acting like actual hardware. From SDM vol3 10.8.4: "Upon acceptance of an interrupt into the IRR, the corresponding TMR bit is cleared for edge-triggered interrupts and set for leveltriggered interrupts." This commit change the ACRN implementation to set/clear corresponding TMR bit when inject intr to vlapic. Tracked-On: #2343 Signed-off-by: Yan, Like <like.yan@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2019-01-17 08:48:22 +08:00
..
x86	hv: set/clear TMR bit like hardware behave	2019-01-17 08:48:22 +08:00