mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-04 22:47:00 +00:00
f347d15e7d
Per SDM Vol. 2:
If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
number supported should come from this field.
This patch gets the maximum physical address number from CPUID leaf
0x80000008 and calculates the physical address mask when the leaf is
available.
Currently ACRN does not support platforms w/o this leaf and will panic
on such platforms.
Also call get_cpu_capabilities() earlier since the physical address mask
is required for initializing paging.
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
398 lines
16 KiB
C
398 lines
16 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef MMU_H
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#define MMU_H
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/* Size of all page-table entries (in bytes) */
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#define IA32E_COMM_ENTRY_SIZE 8
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/* Definitions common for all IA-32e related paging entries */
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#define IA32E_COMM_P_BIT 0x0000000000000001
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#define IA32E_COMM_RW_BIT 0x0000000000000002
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#define IA32E_COMM_US_BIT 0x0000000000000004
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#define IA32E_COMM_PWT_BIT 0x0000000000000008
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#define IA32E_COMM_PCD_BIT 0x0000000000000010
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#define IA32E_COMM_A_BIT 0x0000000000000020
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#define IA32E_COMM_XD_BIT 0x8000000000000000
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/* Defines for EPT paging entries */
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#define IA32E_EPT_R_BIT 0x0000000000000001
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#define IA32E_EPT_W_BIT 0x0000000000000002
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#define IA32E_EPT_X_BIT 0x0000000000000004
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#define IA32E_EPT_UNCACHED (0<<3)
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#define IA32E_EPT_WC (1<<3)
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#define IA32E_EPT_WT (4<<3)
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#define IA32E_EPT_WP (5<<3)
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#define IA32E_EPT_WB (6<<3)
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#define IA32E_EPT_PAT_IGNORE 0x0000000000000040
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#define IA32E_EPT_ACCESS_FLAG 0x0000000000000100
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#define IA32E_EPT_DIRTY_FLAG 0x0000000000000200
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#define IA32E_EPT_SNOOP_CTRL 0x0000000000000800
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#define IA32E_EPT_SUPPRESS_VE 0x8000000000000000
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/* Definitions common or ignored for all IA-32e related paging entries */
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#define IA32E_COMM_D_BIT 0x0000000000000040
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#define IA32E_COMM_G_BIT 0x0000000000000100
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/* Definitions exclusive to a Page Map Level 4 Entry (PML4E) */
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#define IA32E_PML4E_INDEX_MASK_START 39
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#define IA32E_PML4E_ADDR_MASK 0x0000FF8000000000
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/* Definitions exclusive to a Page Directory Pointer Table Entry (PDPTE) */
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#define IA32E_PDPTE_D_BIT 0x0000000000000040
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#define IA32E_PDPTE_PS_BIT 0x0000000000000080
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#define IA32E_PDPTE_PAT_BIT 0x0000000000001000
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#define IA32E_PDPTE_ADDR_MASK 0x0000FFFFC0000000
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#define IA32E_PDPTE_INDEX_MASK_START \
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(IA32E_PML4E_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
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/* Definitions exclusive to a Page Directory Entry (PDE) 1G or 2M */
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#define IA32E_PDE_D_BIT 0x0000000000000040
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#define IA32E_PDE_PS_BIT 0x0000000000000080
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#define IA32E_PDE_PAT_BIT 0x0000000000001000
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#define IA32E_PDE_ADDR_MASK 0x0000FFFFFFE00000
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#define IA32E_PDE_INDEX_MASK_START \
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(IA32E_PDPTE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
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/* Definitions exclusive to Page Table Entries (PTE) */
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#define IA32E_PTE_D_BIT 0x0000000000000040
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#define IA32E_PTE_PAT_BIT 0x0000000000000080
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#define IA32E_PTE_G_BIT 0x0000000000000100
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#define IA32E_PTE_ADDR_MASK 0x0000FFFFFFFFF000
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#define IA32E_PTE_INDEX_MASK_START \
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(IA32E_PDE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
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/** The 'Present' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_P 0x00000001
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/** The 'Read/Write' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_RW 0x00000002
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/** The 'User/Supervisor' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_US 0x00000004
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/** The 'Page Write Through' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_PWT 0x00000008
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/** The 'Page Cache Disable' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_PCD 0x00000010
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/** The 'Accessed' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_A 0x00000020
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/** The 'Dirty' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_D 0x00000040
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/** The 'Page Size' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_PS 0x00000080
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/** The 'Global' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_G 0x00000100
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/** The 'PAT' bit in a page 32 bit paging directory entry */
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#define MMU_32BIT_PDE_PAT 0x00001000
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/** The flag that indicates that the page fault was caused by a non present
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* page.
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*/
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#define PAGE_FAULT_P_FLAG 0x00000001
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/** The flag that indicates that the page fault was caused by a write access. */
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#define PAGE_FAULT_WR_FLAG 0x00000002
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/** The flag that indicates that the page fault was caused in user mode. */
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#define PAGE_FAULT_US_FLAG 0x00000004
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/** The flag that indicates that the page fault was caused by a reserved bit
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* violation.
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*/
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#define PAGE_FAULT_RSVD_FLAG 0x00000008
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/** The flag that indicates that the page fault was caused by an instruction
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* fetch.
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*/
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#define PAGE_FAULT_ID_FLAG 0x00000010
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/* Defines used for common memory sizes */
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#define MEM_1K 1024UL
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#define MEM_2K (MEM_1K * 2UL)
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#define MEM_4K (MEM_1K * 4UL)
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#define MEM_8K (MEM_1K * 8UL)
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#define MEM_16K (MEM_1K * 16UL)
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#define MEM_32K (MEM_1K * 32UL)
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#define MEM_64K (MEM_1K * 64UL)
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#define MEM_128K (MEM_1K * 128UL)
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#define MEM_256K (MEM_1K * 256UL)
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#define MEM_512K (MEM_1K * 512UL)
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#define MEM_1M (MEM_1K * 1024UL)
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#define MEM_2M (MEM_1M * 2UL)
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#define MEM_4M (MEM_1M * 4UL)
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#define MEM_8M (MEM_1M * 8UL)
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#define MEM_16M (MEM_1M * 16UL)
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#define MEM_32M (MEM_1M * 32UL)
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#define MEM_64M (MEM_1M * 64UL)
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#define MEM_128M (MEM_1M * 128UL)
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#define MEM_256M (MEM_1M * 256UL)
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#define MEM_512M (MEM_1M * 512UL)
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#define MEM_1G (MEM_1M * 1024UL)
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#define MEM_2G (MEM_1G * 2UL)
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#define MEM_3G (MEM_1G * 3UL)
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#define MEM_4G (MEM_1G * 4UL)
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#define MEM_5G (MEM_1G * 5UL)
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#define MEM_6G (MEM_1G * 6UL)
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#ifndef ASSEMBLER
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#include <cpu.h>
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/* Define cache line size (in bytes) */
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#define CACHE_LINE_SIZE 64
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/* Size of all page structures for IA-32e */
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#define IA32E_STRUCT_SIZE MEM_4K
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/* IA32E Paging constants */
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#define IA32E_INDEX_MASK_BITS 9
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#define IA32E_NUM_ENTRIES 512
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#define IA32E_INDEX_MASK (uint64_t)(IA32E_NUM_ENTRIES - 1)
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#define IA32E_REF_MASK \
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(boot_cpu_data.physical_address_mask)
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#define IA32E_FIRST_BLOCK_INDEX 1
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/* Macro to get PML4 index given an address */
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#define IA32E_PML4E_INDEX_CALC(address) \
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(uint32_t)((((uint64_t)address >> IA32E_PML4E_INDEX_MASK_START) & \
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IA32E_INDEX_MASK) * sizeof(uint64_t))
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/* Macro to get PDPT index given an address */
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#define IA32E_PDPTE_INDEX_CALC(address) \
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(uint32_t)((((uint64_t)address >> IA32E_PDPTE_INDEX_MASK_START) & \
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IA32E_INDEX_MASK) * sizeof(uint64_t))
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/* Macro to get PD index given an address */
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#define IA32E_PDE_INDEX_CALC(address) \
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(uint32_t)((((uint64_t)address >> IA32E_PDE_INDEX_MASK_START) & \
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IA32E_INDEX_MASK) * sizeof(uint64_t))
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/* Macro to get PT index given an address */
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#define IA32E_PTE_INDEX_CALC(address) \
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(uint32_t)((((uint64_t)address >> IA32E_PTE_INDEX_MASK_START) & \
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IA32E_INDEX_MASK) * sizeof(uint64_t))
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/* Macro to obtain a 2 MB page offset from given linear address */
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#define IA32E_GET_2MB_PG_OFFSET(address) \
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(address & 0x001FFFFF)
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/* Macro to obtain a 4KB page offset from given linear address */
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#define IA32E_GET_4KB_PG_OFFSET(address) \
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(address & 0x00000FFF)
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/*
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* The following generic attributes MMU_MEM_ATTR_FLAG_xxx may be OR'd with one
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* and only one of the MMU_MEM_ATTR_TYPE_xxx definitions
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*/
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/* Generic memory attributes */
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#define MMU_MEM_ATTR_READ 0x00000001
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#define MMU_MEM_ATTR_WRITE 0x00000002
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#define MMU_MEM_ATTR_EXECUTE 0x00000004
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#define MMU_MEM_ATTR_USER 0x00000008
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#define MMU_MEM_ATTR_WB_CACHE 0x00000040
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#define MMU_MEM_ATTR_WT_CACHE 0x00000080
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#define MMU_MEM_ATTR_UNCACHED 0x00000100
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#define MMU_MEM_ATTR_WC 0x00000200
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#define MMU_MEM_ATTR_WP 0x00000400
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/* Definitions for memory types related to x64 */
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#define MMU_MEM_ATTR_BIT_READ_WRITE IA32E_COMM_RW_BIT
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#define MMU_MEM_ATTR_BIT_USER_ACCESSIBLE IA32E_COMM_US_BIT
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#define MMU_MEM_ATTR_BIT_EXECUTE_DISABLE IA32E_COMM_XD_BIT
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/* Selection of Page Attribute Table (PAT) entries with PAT, PCD and PWT
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* encoding. See also pat.h
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*/
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/* Selects PAT0 WB */
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#define MMU_MEM_ATTR_TYPE_CACHED_WB (0x0000000000000000)
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/* Selects PAT1 WT */
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#define MMU_MEM_ATTR_TYPE_CACHED_WT (IA32E_COMM_PWT_BIT)
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/* Selects PAT2 UCM */
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#define MMU_MEM_ATTR_TYPE_UNCACHED_MINUS (IA32E_COMM_PCD_BIT)
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/* Selects PAT3 UC */
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#define MMU_MEM_ATTR_TYPE_UNCACHED \
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(IA32E_COMM_PCD_BIT | IA32E_COMM_PWT_BIT)
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/* Selects PAT6 WC */
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#define MMU_MEM_ATTR_TYPE_WRITE_COMBINED \
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(IA32E_PDPTE_PAT_BIT | IA32E_COMM_PCD_BIT)
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/* Selects PAT7 WP */
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#define MMU_MEM_ATTR_TYPE_WRITE_PROTECTED \
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(IA32E_PDPTE_PAT_BIT | IA32E_COMM_PCD_BIT | IA32E_COMM_PWT_BIT)
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#define ROUND_PAGE_UP(addr) (((addr) + CPU_PAGE_SIZE - 1) & CPU_PAGE_MASK)
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#define ROUND_PAGE_DOWN(addr) ((addr) & CPU_PAGE_MASK)
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struct map_params {
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/* enum _page_table_type: HOST or EPT*/
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int page_table_type;
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/* used HVA->HPA for HOST, used GPA->HPA for EPT */
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void *pml4_base;
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/* used HPA->HVA for HOST, used HPA->GPA for EPT */
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void *pml4_inverted;
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};
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struct entry_params {
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uint32_t entry_level;
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uint32_t entry_present;
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uint64_t entry_base;
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uint64_t entry_off;
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uint64_t entry_val;
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uint64_t page_size;
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};
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enum _page_table_type {
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PTT_HOST = 0, /* Mapping for hypervisor */
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PTT_EPT = 1,
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PAGETABLE_TYPE_UNKNOWN,
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};
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/* Represent the 4 levels of translation tables in IA-32e paging mode */
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enum _page_table_level {
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IA32E_PML4 = 0,
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IA32E_PDPT = 1,
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IA32E_PD = 2,
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IA32E_PT = 3,
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IA32E_UNKNOWN,
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};
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/* Page table entry present */
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enum _page_table_present {
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PT_NOT_PRESENT = 0,
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PT_PRESENT = 1,
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};
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/* Page size */
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#define PAGE_SIZE_4K MEM_4K
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#define PAGE_SIZE_2M MEM_2M
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#define PAGE_SIZE_1G MEM_1G
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/* Macros for reading/writing memory */
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#define MEM_READ8(addr) (*(volatile uint8_t *)(addr))
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#define MEM_WRITE8(addr, data) \
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(*(volatile uint8_t *)(addr) = (uint8_t)(data))
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#define MEM_READ16(addr) (*(volatile uint16_t *)(addr))
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#define MEM_WRITE16(addr, data) \
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(*(volatile uint16_t *)(addr) = (uint16_t)(data))
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#define MEM_READ32(addr) (*(volatile uint32_t *)(addr))
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#define MEM_WRITE32(addr, data) \
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(*(volatile uint32_t *)(addr) = (uint32_t)(data))
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#define MEM_READ64(addr) (*(volatile uint64_t *)(addr))
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#define MEM_WRITE64(addr, data) \
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(*(volatile uint64_t *)(addr) = (uint64_t)(data))
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/* Typedef for MMIO handler and range check routine */
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typedef int(*hv_mem_io_handler_t)(struct vcpu *, struct mem_io *, void *);
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/* Structure for MMIO handler node */
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struct mem_io_node {
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hv_mem_io_handler_t read_write;
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void *handler_private_data;
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struct list_head list;
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uint64_t range_start;
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uint64_t range_end;
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};
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void *get_paging_pml4(void);
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void *alloc_paging_struct(void);
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void enable_paging(void *pml4_base_addr);
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void init_paging(void);
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void map_mem(struct map_params *map_params, void *paddr, void *vaddr,
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uint64_t size, uint32_t flags);
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void unmap_mem(struct map_params *map_params, void *paddr, void *vaddr,
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uint64_t size, uint32_t flags);
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void modify_mem(struct map_params *map_params, void *paddr, void *vaddr,
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uint64_t size, uint32_t flags);
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void mmu_invept(struct vcpu *vcpu);
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void obtain_last_page_table_entry(struct map_params *map_params,
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struct entry_params *entry, void *addr, bool direct);
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int register_mmio_emulation_handler(struct vm *vm,
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hv_mem_io_handler_t read_write, uint64_t start,
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uint64_t end, void *handler_private_data);
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void unregister_mmio_emulation_handler(struct vm *vm, uint64_t start,
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uint64_t end);
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#pragma pack(1)
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/** Defines a single entry in an E820 memory map. */
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struct e820_entry {
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/** The base address of the memory range. */
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uint64_t baseaddr;
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/** The length of the memory range. */
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uint64_t length;
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/** The type of memory region. */
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uint32_t type;
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};
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#pragma pack()
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/* E820 memory types */
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#define E820_TYPE_RAM 1 /* EFI 1, 2, 3, 4, 5, 6, 7 */
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#define E820_TYPE_RESERVED 2
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/* EFI 0, 11, 12, 13 (everything not used elsewhere) */
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#define E820_TYPE_ACPI_RECLAIM 3 /* EFI 9 */
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#define E820_TYPE_ACPI_NVS 4 /* EFI 10 */
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#define E820_TYPE_UNUSABLE 5 /* EFI 8 */
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/** Calculates the page table address for a given address.
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*
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* @param pd The base address of the page directory.
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* @param vaddr The virtual address to calculate the page table address for.
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*
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* @return A pointer to the page table for the specified virtual address.
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*
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*/
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static inline void *mmu_pt_for_pde(uint32_t *pd, uint32_t vaddr)
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{
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return pd + ((vaddr >> 22) + 1) * 1024;
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}
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#define CACHE_FLUSH_INVALIDATE_ALL() \
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{ \
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asm volatile (" wbinvd\n" : : : "memory"); \
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}
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/* External variable declarations */
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extern uint8_t CPU_Boot_Page_Tables_Start_VM[];
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/* External Interfaces */
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int is_ept_supported(void);
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void *create_guest_paging(struct vm *vm);
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void destroy_ept(struct vm *vm);
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uint64_t gpa2hpa(struct vm *vm, uint64_t gpa);
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uint64_t gpa2hpa_check(struct vm *vm, uint64_t gpa,
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uint64_t size, int *found, bool assert);
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uint64_t hpa2gpa(struct vm *vm, uint64_t hpa);
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int ept_mmap(struct vm *vm, uint64_t hpa,
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uint64_t gpa, uint64_t size, uint32_t type, uint32_t prot);
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int ept_violation_handler(struct vcpu *vcpu);
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int ept_misconfig_handler(struct vcpu *vcpu);
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int dm_emulate_mmio_post(struct vcpu *vcpu);
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#endif /* ASSEMBLER not defined */
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#endif /* MMU_H */
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