Sainath Grandhi f3cf93656a hv: Handle holes in GSI i.e. Global System Interrupt for multiple IO-APICs ... MADT is used to specify the GSI base for each IO-APIC and the number of interrupt pins per IO-APIC is programmed into Max. Redir. Entry register of that IO-APIC. On platforms with multiple IO-APICs, there can be holes in the GSI space. For example, on a platform with 2 IO-APICs, the following configuration has a hole (from 24 to 31) in the GSI space. IO-APIC 1: GSI base - 0, number of pins - 24 IO-APIC 2: GSI base - 32, number of pins - 8 This patch also adjusts the size for variables used to represent the total number of IO-APICs on the system from uint16_t to uint8_t as the ACPI MADT uses only 8-bits to indicate the unique IO-APIC IDs. Tracked-On: #4151 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>		2020-04-13 11:39:58 +08:00
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event.c	hv: reset vcpu events in reset_vcpu	2020-02-23 16:27:57 +08:00
hv_main.c	hv: HLT emulation in hypervisor	2020-01-07 11:23:32 +08:00
hypercall.c	hv: Handle holes in GSI i.e. Global System Interrupt for multiple IO-APICs	2020-04-13 11:39:58 +08:00
ptdev.c	hv: rename BOOT_CPU_ID to BSP_CPU_ID	2020-02-25 09:08:14 +08:00
sched_bvt.c	hv: sched_bvt: add tick hanlder	2020-02-25 09:11:32 +08:00
sched_iorr.c	hv: sched_iorr: add some interfaces implementation of sched_iorr	2019-12-11 09:31:39 +08:00
sched_noop.c	hv: sched: decouple scheduler from schedule framework	2019-10-25 13:00:21 +08:00
schedule.c	hv: sched_bvt: add BVT scheduler	2020-02-25 09:11:32 +08:00
softirq.c	softirq: move softirq from hv_main to interrupt context	2019-07-22 09:55:06 +08:00
trusty_hypercall.c	hv: rename the ACRN_DBG_XXX	2020-01-14 10:21:23 +08:00
vm_load.c	HV: init efi info with multiboot2	2020-02-26 09:24:16 +08:00