Yu Wang f42878ee3a hv: apicv: improve the default apicv reset flow ...

Two improvements:

Firstly, disable EOI VMEXIT for all vectors by default. Only the level
sensitive irq need to set it due to need emulate send EOI to vioapic to
clear Remote IRR bit.

Secondly, to clear RVI(Requesting virtual interrupt) and SVI(Servicing
virtual interrupt) bits.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>

2018-08-06 12:32:35 +08:00

..

x86

hv: apicv: improve the default apicv reset flow

2018-08-06 12:32:35 +08:00