Zide Chen f5744174b5 hv: nested: support for VMPTRLD emulation ... This patch emulates the VMPTRLD instruction. L0 hypervisor (ACRN) caches the VMCS12 that is passed down from the VMPTRLD instruction, and merges it with VMCS01 to create VMCS02 to run the nested VM. - Currently ACRN can't cache multiple VMCS12 on one vCPU, so it needs to flushes active but not current VMCS12s to L1 guest. - ACRN creates VMCS02 to run nested VM based on VMCS12: 1) copy VMCS12 from guest memory to the per vCPU cache VMCS12 2) initialize VMCS02 revision ID and host-state area 3) load shadow fields from cache VMCS12 to VMCS02 4) enable VMCS shadowing before L1 Vm entry Tracked-On: #5923 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com>		2021-05-24 10:34:01 +08:00
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arch/x86/asm	hv: nested: support for VMPTRLD emulation	2021-05-24 10:34:01 +08:00
common	hv/mod_timer: refine timer interface	2021-05-18 16:43:28 +08:00
debug	hv: mod: do not use explicit arch name when including headers	2021-05-08 11:15:46 +08:00
dm	hv: PTM: Create virtual root port	2021-05-19 13:54:24 +08:00
hw	hv: PTM: Create virtual root port	2021-05-19 13:54:24 +08:00
lib	hv: bugfix in min() and max() MACROs	2021-04-23 09:58:21 +08:00
public	dm: PTM: Add virtual root port to vm	2021-05-19 13:54:24 +08:00