Chenli Wei 6d56816e79 misc: modify the logic of generate HV_RAM_START ... The current code assume that there must be an HV_RAM_START element in the scenario and we will generate it if user have not set, the default value of HV_RAM_START is 0x00400000 which cause an overlap issue. This patch remove the requires of HV_RAM_START element, calculate HV_RAM_SIZE and find a region of e820 to run the ACRN which start address will be HV_RAM_START. It is still valid if the user set HV_RAM_START by XMLs. Tracked-On: #6690 Signed-off-by: Chenli Wei <chenli.wei@intel.com>		2022-06-07 18:19:39 +08:00
..
lib	misc: configurator: Add entry "None" to HV console selector	2022-05-24 17:14:38 +08:00
bdf.py	config-tools: Fix Enable SR-IOV build fail	2022-05-24 16:07:16 +08:00
board_capability.py	misc: add the define of MAX_IR_ENTRIES	2022-05-20 09:08:47 +08:00
clos.py	misc: refine CLOS module for expansibility	2022-05-11 17:00:51 +08:00
cpu_affinity.py	config_tools: track whether each vCPU is used for real-time or not	2022-04-21 10:08:53 +08:00
gpa.py	config-tools: extract the SSRAM area size	2022-04-18 16:47:23 +08:00
guest_flags.py	misc: set PMU_PT flag for pre-launched RTVM	2022-03-29 09:34:17 +08:00
hv_ram.py	misc: modify the logic of generate HV_RAM_START	2022-06-07 18:19:39 +08:00
intx.py	misc: fix the conflict between S5 and LPC	2022-06-06 22:26:23 +08:00
main.py	misc: fix the issue of create hv node	2022-04-28 13:42:54 +08:00
memory_allocator.py	config_tools: update the hugepage algorithm	2022-05-07 10:51:10 +08:00
pio.py	Remove "All rights reserved" string headers	2022-04-06 13:21:02 +08:00
s5_vuart.py	misc: fix the conflict between S5 and LPC	2022-06-06 22:26:23 +08:00