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https://github.com/projectacrn/acrn-hypervisor.git
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037c479221
Since there is no common IPI abstraction, the arch_ prefix is redundant.
This patch renames the functions as follows:
- arch_send_dest_ipi_mask -> send_dest_ipi_mask
- arch_send_single_ipi -> send_single_ipi
Tracked-On: #8799
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <types.h>
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#include <asm/sbi.h>
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#include <debug/logmsg.h>
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/**
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* An ECALL is used as the control transfer instruction between the
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* supervisor and the SEE.
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*
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* a7 encodes the SBI extension ID (EID).
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*
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* a6 encodes the SBI function ID (FID) for a given extension ID
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* encoded in a7 for any SBI extension defined in or after SBI v0.2.
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*
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* a0 through a5 contain the arguments for the SBI function call.
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* Registers that are not defined in the SBI function call are not
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* reserved.
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*
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* All registers except a0 & a1 must be preserved across an SBI call
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* by the callee.
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*
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* SBI functions must return a pair of values in a0 and a1, with a0
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* returning an error code. This is analogous to returning the C
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* structure.
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*/
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static sbiret sbi_ecall(uint64_t arg0, uint64_t arg1, uint64_t arg2,
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uint64_t arg3, uint64_t arg4, uint64_t arg5,
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uint64_t func, uint64_t ext)
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{
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sbiret ret;
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register uint64_t a0 asm ("a0") = arg0;
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register uint64_t a1 asm ("a1") = arg1;
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register uint64_t a2 asm ("a2") = arg2;
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register uint64_t a3 asm ("a3") = arg3;
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register uint64_t a4 asm ("a4") = arg4;
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register uint64_t a5 asm ("a5") = arg5;
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register uint64_t a6 asm ("a6") = func;
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register uint64_t a7 asm ("a7") = ext;
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asm volatile (
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"ecall \n\t"
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:"+r" (a0), "+r" (a1)
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:"r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
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: "memory"
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);
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ret.error = a0;
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ret.value = a1;
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return ret;
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}
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/**
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* Implemented IPI functionality using the SBI IPI Extension (EID #0x735049).
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* Legacy SBI extensions are not supported in ACRN.
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*/
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static int64_t sbi_send_ipi(uint64_t mask, uint64_t mask_base)
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{
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sbiret ret = sbi_ecall(mask, mask_base, 0UL, 0UL, 0UL, 0UL, SBI_IPI_FID_SEND_IPI, SBI_EID_IPI);
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if (ret.error != SBI_SUCCESS) {
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pr_err("%s: Failed to send IPI by SBI, error code: %lx", __func__, ret.error);
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}
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return ret.error;
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}
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/**
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* msg_type is currently unused.
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*
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* At present, only IPI_NOTIFY_CPU is supported, covering two use cases:
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* - SMP call
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* - Kick pCPU out of non-root mode
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*
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* Callers should invoke this function with:
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* send_single_ipi(pcpu_id, IPI_NOTIFY_CPU);
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*
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* msg_type is retained for future extensions and to stay aligned with
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* the function prototype used on other architectures (e.g. x86).
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*/
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void send_single_ipi(uint16_t pcpu_id, __unused uint32_t msg_type)
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{
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sbi_send_ipi((1UL << pcpu_id), 0UL);
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}
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/**
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* Similar to send_single_ipi() regards to msg_type.
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*
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* Callers should invoke this function with:
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* send_dest_ipi_mask(dest_mask, IPI_NOTIFY_CPU);
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*/
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void send_dest_ipi_mask(uint64_t dest_mask, __unused uint32_t msg_type)
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{
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sbi_send_ipi(dest_mask, 0UL);
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}
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/**
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* Implemented Timer functionality using the SBI Timer Extension (EID #0x54494D45).
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*/
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int sbi_set_timer(uint64_t stime_value)
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{
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sbiret ret = sbi_ecall(stime_value, 0, 0, 0, 0, 0, SBI_TIMER_FID_SET_TIMER, SBI_EID_TIMER);
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if (ret.error != SBI_SUCCESS) {
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pr_err("%s: Failed to set Timer by SBI, error code: %lx", __func__, ret.error);
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}
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return ret.error;
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}
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