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f67a437e5a
extract common barrier interface to include/lib/barrier.h, and invoke the variant implementation of arch. Tracked-On: #8803 Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
27 lines
634 B
C
27 lines
634 B
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef X86_LIB_BARRIER_H
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#define X86_LIB_BARRIER_H
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/* Synchronizes all read accesses to memory */
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static inline void arch_cpu_read_memory_barrier(void)
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{
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asm volatile ("lfence\n" : : : "memory");
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}
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/* Synchronizes all write accesses to memory */
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static inline void arch_cpu_write_memory_barrier(void)
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{
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asm volatile ("sfence\n" : : : "memory");
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}
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/* Synchronizes all read and write accesses to/from memory */
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static inline void arch_cpu_memory_barrier(void)
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{
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asm volatile ("mfence\n" : : : "memory");
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}
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#endif /* X86_LIB_BARRIER_H */
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