Fei Li f687574a58 vuart: add dummy vuart for risc-v ...

vUART will not enable before VM could be created.

Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

2025-10-14 14:45:12 +08:00

..

guest

vuart: add dummy vuart for risc-v

2025-10-14 14:45:12 +08:00

lib

hv: multi-arch add RISC-V bits library implementation

2025-09-22 10:52:06 +08:00

cpu.h

smap: risc-v should implement enable and disable APIs

2025-10-14 14:45:12 +08:00

init.h

…

io.h

io: add risc-v mmio read and write APIs with memory order

2025-10-09 17:15:06 +08:00

irq.h

hv: riscv: irq: add interrupt initialization and handlers

2025-09-29 14:01:00 +08:00

mmu.h

mmu: add dummy APIs for risc-v

2025-10-14 14:45:12 +08:00

notify.h

…

offset.h

hv: riscv: fix stack allocation in cpu_ctx_save/cpu_ctx_restore

2025-10-14 09:45:17 +08:00

page.h

mmu: add dummy APIs for risc-v

2025-10-14 14:45:12 +08:00

per_cpu.h

hv: riscv: add get/set_pcpu_id and start_pcpus implementation

2025-09-23 11:30:38 +08:00

pgtable.h

mmu: add dummy APIs for risc-v

2025-10-14 14:45:12 +08:00

qemu.h

…

sbi.h

hv: riscv: add SBI HSM HART_START interface

2025-09-23 11:30:38 +08:00

security.h

hv: multiarch: riscv: add dummy header for riscv

2025-09-19 15:04:55 +08:00

timer.h

…

trap.h

hv: riscv: irq: add interrupt initialization and handlers

2025-09-29 14:01:00 +08:00

vm_config.h

hv: multiarch: riscv: add dummy header for riscv

2025-09-19 15:04:55 +08:00