Haicheng Li f6bf0b809d risc-v: initial timer codes ...

This patch implements risc-v specific timer codes. Basically,
risc-v adapts to acrn timer framework with some specific
behaviors. So far, it enables sstc support in h-mode.

Tracked-On: #8792
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Co-developed-by: Yong Li <yong.li@intel.com>
Signed-off-by: Yong Li <yong.li@intel.com>
Co-developed-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

2025-09-17 08:55:12 +08:00

..

lib

hv: multi-arch add RISC-V memory library

2025-09-15 14:07:58 +08:00

cpu.h

risc-v: initial timer codes

2025-09-17 08:55:12 +08:00

init.h

hv: risc-v: add C entry function of BSP and APs

2025-09-15 13:12:21 +08:00

irq.h

…

notify.h

hv: smpcall: riscv: implement SMP call handlers

2025-09-09 16:37:04 +08:00

per_cpu.h

hv: smpcall: riscv: implement SMP call handlers

2025-09-09 16:37:04 +08:00

qemu.h

risc-v: initial timer codes

2025-09-17 08:55:12 +08:00

sbi.h

risc-v: add SBI timer interface

2025-09-17 08:55:12 +08:00

timer.h

risc-v: initial timer codes

2025-09-17 08:55:12 +08:00