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a68f655a11
For a pre-launched VM, a region from PTDEV_HI_MMIO_START is used to store 64bit vBARs of PT devices which address is high than 4G. The region should be located after all user memory space and be coverd by guest EPT address. Tracked-On: #4458 Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm_config.h>
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#include <pci_devices.h>
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#include <vpci.h>
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#include <mmu.h>
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#include <page.h>
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/* The vbar_base info of pt devices is included in device MACROs which defined in
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* arch/x86/configs/$(CONFIG_BOARD)/pci_devices.h.
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* The memory range of vBAR should exactly match with the e820 layout of VM.
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*/
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struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
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{
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.emu_type = PCI_DEV_TYPE_HVEMUL,
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.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
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.vdev_ops = &vhostbridge_ops,
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},
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
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VM0_STORAGE_CONTROLLER
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},
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
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VM0_NETWORK_CONTROLLER
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},
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};
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struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = {
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{
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.emu_type = PCI_DEV_TYPE_HVEMUL,
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.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
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.vdev_ops = &vhostbridge_ops,
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},
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
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VM1_STORAGE_CONTROLLER
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},
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#if defined(VM1_NETWORK_CONTROLLER)
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
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VM1_NETWORK_CONTROLLER
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},
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#endif
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};
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